From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: Re: [PATCH 18/19] xen: arm: Annotate registers trapped when CNTHCTL_EL2.EL1PCEN == 0 Date: Fri, 17 Apr 2015 13:12:03 +0100 Message-ID: <1429272723.25195.292.camel@citrix.com> References: <1427796446.2115.34.camel@citrix.com> <1427796462-24376-18-git-send-email-ian.campbell@citrix.com> <55229118.7000405@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <55229118.7000405@gmail.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Julien Grall Cc: julien.grall@linaro.org, tim@xen.org, stefano.stabellini@eu.citrix.com, xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org On Mon, 2015-04-06 at 15:58 +0200, Julien Grall wrote: > Hi Ian, > > On 31/03/2015 12:07, Ian Campbell wrote: > > Signed-off-by: Ian Campbell > > --- > > xen/arch/arm/traps.c | 20 ++++++++++++++++++-- > > 1 file changed, 18 insertions(+), 2 deletions(-) > > > > diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c > > index 1c9cf21..cc5b8dd 100644 > > --- a/xen/arch/arm/traps.c > > +++ b/xen/arch/arm/traps.c > > @@ -1642,6 +1642,12 @@ static void do_cp15_32(struct cpu_user_regs *regs, > > > > switch ( hsr.bits & HSR_CP32_REGS_MASK ) > > { > > + /* > > + * !CNTHCTL_EL2.EL1PCEN / !CNTHCTL.PL1PCEN > > I will be picky. The listing here is ARMv8 (AArch64) / ARMv7, but below > it's ARMv7 / ARMv8. I'm not spotting the "below", which one did you mean? I was trying to use the AArch64 names only when they were reasonably similar (i.e. just differing in H prefix vs _EL2 suffix or otherwise fairly obvious) and only use both names if there was some potentially confusing difference in the naming. > > > + * > > + * ARMv7 (DDI 0406C.b): B4.1.22 > > + * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 > > + */ > > case HSR_CPREG32(CNTP_CTL): > > case HSR_CPREG32(CNTP_TVAL): > > if ( !vtimer_emulate(regs, hsr) ) > > @@ -1757,6 +1763,12 @@ static void do_cp15_64(struct cpu_user_regs *regs, > > > > switch ( hsr.bits & HSR_CP64_REGS_MASK ) > > { > > + /* > > + * !CNTHCTL_EL2.EL1PCEN / !CNTHCTL.PL1PCEN > > + * > > + * ARMv7 (DDI 0406C.b): B4.1.22 > > + * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 > > + */ > > case HSR_CPREG64(CNTP_CVAL): > > if ( !vtimer_emulate(regs, hsr) ) > > return inject_undef_exception(regs, hsr); > > @@ -2120,14 +2132,18 @@ static void do_sysreg(struct cpu_user_regs *regs, > > */ > > return handle_raz_wi(regs, x, hsr.sysreg.read, hsr, 1); > > > > - /* Write only, Write ignore registers: */ > > - > > This comment should have been dropped in patch #14. Moved. Ian.