Re: [PATCH v5 02/13] x86: improve psr scheduling code

[Dario Faggioli <dario.faggioli@citrix.com>]

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On Fri, 2015-04-17 at 22:33 +0800, Chao Peng wrote:
> Switching RMID from previous vcpu to next vcpu only needs to write
> MSR_IA32_PSR_ASSOC once. Write it with the value of next vcpu is enough,
> no need to write '0' first. Idle domain has RMID set to 0 and because MSR
> is already updated lazily, so just switch it as it does.
> 
> Also move the initialization of per-CPU variable which used for lazy
> update from context switch to CPU starting.
> 
> Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
> ---

> --- a/xen/include/asm-x86/psr.h
> +++ b/xen/include/asm-x86/psr.h
> @@ -46,7 +46,8 @@ static inline bool_t psr_cmt_enabled(void)
>  
>  int psr_alloc_rmid(struct domain *d);
>  void psr_free_rmid(struct domain *d);
> -void psr_assoc_rmid(unsigned int rmid);
> +
> +void psr_ctxt_switch_to(struct domain *d);
>
Why the blank line?

Anyway,

Reviewed-by: Dario Faggioli <dario.faggioli@citrix.com>

Regards,
Dario

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