From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linuxfoundation.org ([140.211.169.12]:42884 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751956AbbEBRCc (ORCPT ); Sat, 2 May 2015 13:02:32 -0400 Subject: Patch "clk: tegra: Use the proper parent for plld_dsi" has been added to the 4.0-stable tree To: treding@nvidia.com, gregkh@linuxfoundation.org Cc: , From: Date: Sat, 02 May 2015 19:01:14 +0200 Message-ID: <143058607417359@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: This is a note to let you know that I've just added the patch titled clk: tegra: Use the proper parent for plld_dsi to the 4.0-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: clk-tegra-use-the-proper-parent-for-plld_dsi.patch and it can be found in the queue-4.0 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >>From c1d676cec572544616273d5853cb7cc38fbaa62b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 26 Mar 2015 17:53:01 +0100 Subject: clk: tegra: Use the proper parent for plld_dsi From: Thierry Reding commit c1d676cec572544616273d5853cb7cc38fbaa62b upstream. The current parent, plld_out0, does not exist. The proper name is pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to be more consistent with other clock names. Fixes: b270491eb9a0 ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux") Signed-off-by: Thierry Reding Signed-off-by: Greg Kroah-Hartman --- drivers/clk/tegra/clk-tegra124.c | 14 ++++++++------ include/dt-bindings/clock/tegra124-car-common.h | 2 +- 2 files changed, 9 insertions(+), 7 deletions(-) --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -1110,16 +1110,18 @@ static __init void tegra124_periph_clk_i 1, 2); clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk; - clk = clk_register_gate(NULL, "plld_dsi", "plld_out0", 0, + clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0, clk_base + PLLD_MISC, 30, 0, &pll_d_lock); - clks[TEGRA124_CLK_PLLD_DSI] = clk; + clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk; - clk = tegra_clk_register_periph_gate("dsia", "plld_dsi", 0, clk_base, - 0, 48, periph_clk_enb_refcnt); + clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0, + clk_base, 0, 48, + periph_clk_enb_refcnt); clks[TEGRA124_CLK_DSIA] = clk; - clk = tegra_clk_register_periph_gate("dsib", "plld_dsi", 0, clk_base, - 0, 82, periph_clk_enb_refcnt); + clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0, + clk_base, 0, 82, + periph_clk_enb_refcnt); clks[TEGRA124_CLK_DSIB] = clk; /* emc mux */ --- a/include/dt-bindings/clock/tegra124-car-common.h +++ b/include/dt-bindings/clock/tegra124-car-common.h @@ -297,7 +297,7 @@ #define TEGRA124_CLK_PLL_C4 270 #define TEGRA124_CLK_PLL_DP 271 #define TEGRA124_CLK_PLL_E_MUX 272 -#define TEGRA124_CLK_PLLD_DSI 273 +#define TEGRA124_CLK_PLL_D_DSI_OUT 273 /* 274 */ /* 275 */ /* 276 */ Patches currently in stable-queue which might be from treding@nvidia.com are queue-4.0/clk-tegra-register-the-proper-number-of-resets.patch queue-4.0/clk-tegra-use-the-proper-parent-for-plld_dsi.patch