From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: Re: [PATCH v4 3/3] xen/iommu: arm: Use p2m_ipa_bits as stage2 input size Date: Tue, 5 May 2015 14:24:23 +0100 Message-ID: <1430832263.2660.94.camel@citrix.com> References: <1430444419-11564-1-git-send-email-edgar.iglesias@gmail.com> <1430444419-11564-4-git-send-email-edgar.iglesias@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1430444419-11564-4-git-send-email-edgar.iglesias@gmail.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: "Edgar E. Iglesias" Cc: julien.grall@citrix.com, tim@xen.org, edgar.iglesias@xilinx.com, stefano.stabellini@citrix.com, xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org On Fri, 2015-05-01 at 11:40 +1000, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > The Stage2 input-size must match what the CPU uses because > the SMMU and the CPU share page-tables. > > Test that the SMMU supports the P2M IPA bit size, use it if > supported or bail out if not. > > Signed-off-by: Edgar E. Iglesias > --- > xen/drivers/passthrough/arm/smmu.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c > index 8a9b58b..d9f3931 100644 > --- a/xen/drivers/passthrough/arm/smmu.c > +++ b/xen/drivers/passthrough/arm/smmu.c > @@ -2230,8 +2230,14 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) > size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK); > smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size); > > - /* Xen: Stage-2 input size is not restricted */ > - smmu->s2_input_size = size; > + /* Xen: Stage-2 input size has to match p2m_ipa_bits. */ > + if (size < p2m_ipa_bits) { Referencing my question on 0/3, what if size > p2m_ipa_bits? Do we need to also check that we are configuring the same number of levels of PT etc, or is that already handled? > + dev_err(smmu->dev, > + "P2M IPA size not supported (P2M=%u SMMU=%lu)!\n", > + p2m_ipa_bits, size); > + return -ENODEV; > + } > + smmu->s2_input_size = p2m_ipa_bits; > #if 0 > /* Stage-2 input size limited due to pgd allocation (PTRS_PER_PGD) */ > #ifdef CONFIG_64BIT