Re: [PATCH] drm/i195/bxt: Add A1 stepping for Broxton

[Imre Deak <imre.deak@intel.com>]

On ti, 2015-05-05 at 15:20 +0100, Nick Hoath wrote:
> On 29/04/2015 15:35, Deak, Imre wrote:
> > On pe, 2015-03-20 at 09:29 +0000, Nick Hoath wrote:
> >> This stepping isn't listed separately in the specs, so needs confirmation.
> >>
> >> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/i915_drv.h | 1 +
> >>   1 file changed, 1 insertion(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >> index eec271a..68fb41a 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -2329,6 +2329,7 @@ struct drm_i915_cmd_table {
> >>   #define SKL_REVID_E0		(0x4)
> >>
> >>   #define BXT_REVID_A0		(0x0)
> >> +#define BXT_REVID_A1		(0x1)
> >
> > The above mapping is for the SOC RevID, but I think for all our purposes
> > (WAs) we should check the GT/Display RevID. The A1 GT/Display RevID
> > doesn't seem to exist, only A0 is defined with all of 0,1,2 RevIDs
> > mapping to A0.
> 
> We use the GT Device2 Revision ID for these comparisons, which does 
> change on each SoC revision. This may map to A0 GT stepping for all the 
> Ax SoCs, according to the specs. However, as this is a naming convention 
> that doesn't affect the code, I suggest we stick to what I have in this 
> patch even if it doesn't 100% reflect what's in the specs.

Not sure about this, as I understand all the workarounds are marked with
the GT stepping not the SOC stepping, even though the latter is more
fine-grained. Is there any workarounds for A1? If not I'd suggest adding
this macro only when we need it.

--Imre

> >>   #define BXT_REVID_B0		(0x3)
> >>   #define BXT_REVID_C0		(0x6)
> >>
> >
> >
> 


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx