From: <gregkh@linuxfoundation.org>
To: marc.zyngier@arm.com, catalin.marinas@arm.com,
christoffer.dall@linaro.org, gregkh@linuxfoundation.org,
shannon.zhao@linaro.org
Cc: <stable@vger.kernel.org>, <stable-commits@vger.kernel.org>
Subject: Patch "ARM: KVM: introduce kvm_p*d_addr_end" has been added to the 3.14-stable tree
Date: Fri, 15 May 2015 16:09:20 -0700 [thread overview]
Message-ID: <143173136012166@kroah.com> (raw)
This is a note to let you know that I've just added the patch titled
ARM: KVM: introduce kvm_p*d_addr_end
to the 3.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm-kvm-introduce-kvm_p-d_addr_end.patch
and it can be found in the queue-3.14 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
>From a3c8bd31af260a17d626514f636849ee1cd1f63e Mon Sep 17 00:00:00 2001
From: Marc Zyngier <marc.zyngier@arm.com>
Date: Tue, 18 Feb 2014 14:29:03 +0000
Subject: ARM: KVM: introduce kvm_p*d_addr_end
From: Marc Zyngier <marc.zyngier@arm.com>
commit a3c8bd31af260a17d626514f636849ee1cd1f63e upstream.
The use of p*d_addr_end with stage-2 translation is slightly dodgy,
as the IPA is 40bits, while all the p*d_addr_end helpers are
taking an unsigned long (arm64 is fine with that as unligned long
is 64bit).
The fix is to introduce 64bit clean versions of the same helpers,
and use them in the stage-2 page table code.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/arm/include/asm/kvm_mmu.h | 13 +++++++++++++
arch/arm/kvm/mmu.c | 10 +++++-----
arch/arm64/include/asm/kvm_mmu.h | 4 ++++
3 files changed, 22 insertions(+), 5 deletions(-)
--- a/arch/arm/include/asm/kvm_mmu.h
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -114,6 +114,19 @@ static inline void kvm_set_s2pmd_writabl
pmd_val(*pmd) |= L_PMD_S2_RDWR;
}
+/* Open coded p*d_addr_end that can deal with 64bit addresses */
+#define kvm_pgd_addr_end(addr, end) \
+({ u64 __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \
+ (__boundary - 1 < (end) - 1)? __boundary: (end); \
+})
+
+#define kvm_pud_addr_end(addr,end) (end)
+
+#define kvm_pmd_addr_end(addr, end) \
+({ u64 __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \
+ (__boundary - 1 < (end) - 1)? __boundary: (end); \
+})
+
struct kvm;
static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -147,7 +147,7 @@ static void unmap_range(struct kvm *kvm,
pgd = pgdp + pgd_index(addr);
pud = pud_offset(pgd, addr);
if (pud_none(*pud)) {
- addr = pud_addr_end(addr, end);
+ addr = kvm_pud_addr_end(addr, end);
continue;
}
@@ -157,13 +157,13 @@ static void unmap_range(struct kvm *kvm,
* move on.
*/
clear_pud_entry(kvm, pud, addr);
- addr = pud_addr_end(addr, end);
+ addr = kvm_pud_addr_end(addr, end);
continue;
}
pmd = pmd_offset(pud, addr);
if (pmd_none(*pmd)) {
- addr = pmd_addr_end(addr, end);
+ addr = kvm_pmd_addr_end(addr, end);
continue;
}
@@ -178,10 +178,10 @@ static void unmap_range(struct kvm *kvm,
*/
if (kvm_pmd_huge(*pmd) || page_empty(pte)) {
clear_pmd_entry(kvm, pmd, addr);
- next = pmd_addr_end(addr, end);
+ next = kvm_pmd_addr_end(addr, end);
if (page_empty(pmd) && !page_empty(pud)) {
clear_pud_entry(kvm, pud, addr);
- next = pud_addr_end(addr, end);
+ next = kvm_pud_addr_end(addr, end);
}
}
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -121,6 +121,10 @@ static inline void kvm_set_s2pmd_writabl
pmd_val(*pmd) |= PMD_S2_RDWR;
}
+#define kvm_pgd_addr_end(addr, end) pgd_addr_end(addr, end)
+#define kvm_pud_addr_end(addr, end) pud_addr_end(addr, end)
+#define kvm_pmd_addr_end(addr, end) pmd_addr_end(addr, end)
+
struct kvm;
#define kvm_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
Patches currently in stable-queue which might be from marc.zyngier@arm.com are
queue-3.14/kvm-arm-arm64-vgic-fix-gicd_icfgr-register-accesses.patch
queue-3.14/arm-kvm-introduce-per-vcpu-hyp-configuration-register.patch
queue-3.14/arm-kvm-fix-handling-of-trapped-64bit-coprocessor-accesses.patch
queue-3.14/kvm-arm64-vgic-fix-hyp-panic-with-64k-pages-on-juno-platform.patch
queue-3.14/arm64-kvm-force-cache-clean-on-page-fault-when-caches-are-off.patch
queue-3.14/arm-kvm-introduce-kvm_p-d_addr_end.patch
queue-3.14/arm64-kvm-flush-vm-pages-before-letting-the-guest-enable-caches.patch
queue-3.14/arm-kvm-force-cache-clean-on-page-fault-when-caches-are-off.patch
queue-3.14/arm-kvm-add-world-switch-for-amair-0-1.patch
queue-3.14/kvm-arm-vgic-fix-the-overlap-check-action-about-setting-the-gicd-gicc-base-address.patch
queue-3.14/arm64-kvm-use-inner-shareable-barriers-for-inner-shareable-maintenance.patch
queue-3.14/arm64-kvm-allows-discrimination-of-aarch32-sysreg-access.patch
queue-3.14/arm-kvm-trap-vm-system-registers-until-mmu-and-caches-are-on.patch
queue-3.14/arm-kvm-fix-ordering-of-64bit-coprocessor-accesses.patch
queue-3.14/arm64-kvm-trap-vm-system-registers-until-mmu-and-caches-are-on.patch
reply other threads:[~2015-05-15 23:09 UTC|newest]
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