From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linuxfoundation.org ([140.211.169.12]:42981 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1946170AbbEOXJX (ORCPT ); Fri, 15 May 2015 19:09:23 -0400 Subject: Patch "arm64: KVM: force cache clean on page fault when caches are off" has been added to the 3.14-stable tree To: marc.zyngier@arm.com, catalin.marinas@arm.com, christoffer.dall@linaro.org, gregkh@linuxfoundation.org, shannon.zhao@linaro.org Cc: , From: Date: Fri, 15 May 2015 16:09:22 -0700 Message-ID: <143173136280226@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: This is a note to let you know that I've just added the patch titled arm64: KVM: force cache clean on page fault when caches are off to the 3.14-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: arm64-kvm-force-cache-clean-on-page-fault-when-caches-are-off.patch and it can be found in the queue-3.14 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >>From 2d58b733c87689d3d5144e4ac94ea861cc729145 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Tue, 14 Jan 2014 19:13:10 +0000 Subject: arm64: KVM: force cache clean on page fault when caches are off From: Marc Zyngier commit 2d58b733c87689d3d5144e4ac94ea861cc729145 upstream. In order for the guest with caches off to observe data written contained in a given page, we need to make sure that page is committed to memory, and not just hanging in the cache (as guest accesses are completely bypassing the cache until it decides to enable it). For this purpose, hook into the coherent_icache_guest_page function and flush the region if the guest SCTLR_EL1 register doesn't show the MMU and caches as being enabled. The function also get renamed to coherent_cache_guest_page. Signed-off-by: Marc Zyngier Reviewed-by: Catalin Marinas Reviewed-by: Christoffer Dall Cc: Shannon Zhao Signed-off-by: Greg Kroah-Hartman --- arch/arm/include/asm/kvm_mmu.h | 4 ++-- arch/arm/kvm/mmu.c | 4 ++-- arch/arm64/include/asm/kvm_mmu.h | 16 ++++++++++++---- 3 files changed, 16 insertions(+), 8 deletions(-) --- a/arch/arm/include/asm/kvm_mmu.h +++ b/arch/arm/include/asm/kvm_mmu.h @@ -116,8 +116,8 @@ static inline void kvm_set_s2pmd_writabl struct kvm; -static inline void coherent_icache_guest_page(struct kvm *kvm, hva_t hva, - unsigned long size) +static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva, + unsigned long size) { /* * If we are going to insert an instruction page and the icache is --- a/arch/arm/kvm/mmu.c +++ b/arch/arm/kvm/mmu.c @@ -717,7 +717,7 @@ static int user_mem_abort(struct kvm_vcp kvm_set_s2pmd_writable(&new_pmd); kvm_set_pfn_dirty(pfn); } - coherent_icache_guest_page(kvm, hva & PMD_MASK, PMD_SIZE); + coherent_cache_guest_page(vcpu, hva & PMD_MASK, PMD_SIZE); ret = stage2_set_pmd_huge(kvm, memcache, fault_ipa, &new_pmd); } else { pte_t new_pte = pfn_pte(pfn, PAGE_S2); @@ -725,7 +725,7 @@ static int user_mem_abort(struct kvm_vcp kvm_set_s2pte_writable(&new_pte); kvm_set_pfn_dirty(pfn); } - coherent_icache_guest_page(kvm, hva, PAGE_SIZE); + coherent_cache_guest_page(vcpu, hva, PAGE_SIZE); ret = stage2_set_pte(kvm, memcache, fault_ipa, &new_pte, false); } --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -106,7 +106,6 @@ static inline bool kvm_is_write_fault(un return true; } -static inline void kvm_clean_dcache_area(void *addr, size_t size) {} static inline void kvm_clean_pgd(pgd_t *pgd) {} static inline void kvm_clean_pmd_entry(pmd_t *pmd) {} static inline void kvm_clean_pte(pte_t *pte) {} @@ -124,9 +123,19 @@ static inline void kvm_set_s2pmd_writabl struct kvm; -static inline void coherent_icache_guest_page(struct kvm *kvm, hva_t hva, - unsigned long size) +#define kvm_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l)) + +static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) { + return (vcpu_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; +} + +static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva, + unsigned long size) +{ + if (!vcpu_has_cache_enabled(vcpu)) + kvm_flush_dcache_to_poc((void *)hva, size); + if (!icache_is_aliasing()) { /* PIPT */ flush_icache_range(hva, hva + size); } else if (!icache_is_aivivt()) { /* non ASID-tagged VIVT */ @@ -135,7 +144,6 @@ static inline void coherent_icache_guest } } -#define kvm_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l)) #define kvm_virt_to_phys(x) __virt_to_phys((unsigned long)(x)) #endif /* __ASSEMBLY__ */ Patches currently in stable-queue which might be from marc.zyngier@arm.com are queue-3.14/kvm-arm-arm64-vgic-fix-gicd_icfgr-register-accesses.patch queue-3.14/arm-kvm-introduce-per-vcpu-hyp-configuration-register.patch queue-3.14/arm-kvm-fix-handling-of-trapped-64bit-coprocessor-accesses.patch queue-3.14/kvm-arm64-vgic-fix-hyp-panic-with-64k-pages-on-juno-platform.patch queue-3.14/arm64-kvm-force-cache-clean-on-page-fault-when-caches-are-off.patch queue-3.14/arm-kvm-introduce-kvm_p-d_addr_end.patch queue-3.14/arm64-kvm-flush-vm-pages-before-letting-the-guest-enable-caches.patch queue-3.14/arm-kvm-force-cache-clean-on-page-fault-when-caches-are-off.patch queue-3.14/arm-kvm-add-world-switch-for-amair-0-1.patch queue-3.14/kvm-arm-vgic-fix-the-overlap-check-action-about-setting-the-gicd-gicc-base-address.patch queue-3.14/arm64-kvm-use-inner-shareable-barriers-for-inner-shareable-maintenance.patch queue-3.14/arm64-kvm-allows-discrimination-of-aarch32-sysreg-access.patch queue-3.14/arm-kvm-trap-vm-system-registers-until-mmu-and-caches-are-on.patch queue-3.14/arm-kvm-fix-ordering-of-64bit-coprocessor-accesses.patch queue-3.14/arm64-kvm-trap-vm-system-registers-until-mmu-and-caches-are-on.patch