Re: [PATCH v2 0/8] ASoC: Intel: refactor common SST IPC handling

[Liam Girdwood <liam.r.girdwood@linux.intel.com>]

On Tue, 2015-05-19 at 15:00 +0530, Vinod Koul wrote:
> This series refactors the common SST IPC code to remove some hardcoded
> assumption which are no longer valid for future platforms like Skylake,
> These are made configurable and right configuration applied for respective
> drivers. The changes are mailbox sizes and dsp busy checks.
> 
> changes in v2:
>  - fix the mem allocation for IPC mailbox
> 
> Subhransu S. Prusty (8):
>   ASoC: Intel: Create an ops to check for DSP busy
>   ASoC: Intel: Move the busy check to ops for Baytrail
>   ASoC: Intel: Move the busy check to ops for HSW
>   ASoC: Intel: Remove the direct register reference from common ipc
>   ASoC: Intel: Allow to configure max size for mailbox data
>   ASoC: Intel: Initialize max mailbox size for baytrail
>   ASoC: Intel: Initialize max mailbox size for haswell
>   ASoC: Intel: Allocate for the mailbox with max size
> 
>  sound/soc/intel/baytrail/sst-baytrail-ipc.c | 11 ++++++++++
>  sound/soc/intel/common/sst-ipc.c            | 34 +++++++++++++++++++++++++----
>  sound/soc/intel/common/sst-ipc.h            |  7 ++++--
>  sound/soc/intel/haswell/sst-haswell-ipc.c   | 12 ++++++++++
>  4 files changed, 58 insertions(+), 6 deletions(-)
> 

Acked-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>