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From: Marcel Apfelbaum <marcel@redhat.com>
To: qemu-devel@nongnu.org
Cc: marcel@redhat.com, mst@redhat.com
Subject: [Qemu-devel] [PATCH V8 07/17] hw/apci: add _PRT method for extra PCI root busses
Date: Tue,  2 Jun 2015 14:23:02 +0300	[thread overview]
Message-ID: <1433244192-27624-8-git-send-email-marcel@redhat.com> (raw)
In-Reply-To: <1433244192-27624-1-git-send-email-marcel@redhat.com>

Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
---
 hw/i386/acpi-build.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index a7e248d..451566f 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -617,6 +617,86 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
     aml_append(parent_scope, method);
 }
 
+/*
+ * initialize_route - Initialize the interrupt routing rule
+ * through a specific LINK:
+ *  if (lnk_idx == idx)
+ *      route using link 'link_name'
+ */
+static Aml *initialize_route(Aml *route, const char *link_name,
+                             Aml *lnk_idx, int idx)
+{
+    Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
+    Aml *pkg = aml_package(4);
+
+    aml_append(pkg, aml_int(0));
+    aml_append(pkg, aml_int(0));
+    aml_append(pkg, aml_name("%s", link_name));
+    aml_append(pkg, aml_int(0));
+    aml_append(if_ctx, aml_store(pkg, route));
+
+    return if_ctx;
+}
+
+/*
+ * build_prt - Define interrupt rounting rules
+ *
+ * Returns an array of 128 routes, one for each device,
+ * based on device location.
+ * The main goal is to equaly distribute the interrupts
+ * over the 4 existing ACPI links (works only for i440fx).
+ * The hash function is  (slot + pin) & 3 -> "LNK[D|A|B|C]".
+ *
+ */
+static Aml *build_prt(void)
+{
+    Aml *method, *while_ctx, *pin, *res;
+
+    method = aml_method("_PRT", 0);
+    res = aml_local(0);
+    pin = aml_local(1);
+    aml_append(method, aml_store(aml_package(128), res));
+    aml_append(method, aml_store(aml_int(0), pin));
+
+    /* while (pin < 128) */
+    while_ctx = aml_while(aml_lless(pin, aml_int(128)));
+    {
+        Aml *slot = aml_local(2);
+        Aml *lnk_idx = aml_local(3);
+        Aml *route = aml_local(4);
+
+        /* slot = pin >> 2 */
+        aml_append(while_ctx,
+                   aml_store(aml_shiftright(pin, aml_int(2)), slot));
+        /* lnk_idx = (slot + pin) & 3 */
+        aml_append(while_ctx,
+                   aml_store(aml_and(aml_add(pin, slot), aml_int(3)), lnk_idx));
+
+        /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3  */
+        aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
+        aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
+        aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
+        aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
+
+        /* route[0] = 0x[slot]FFFF */
+        aml_append(while_ctx,
+            aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF)),
+                      aml_index(route, aml_int(0))));
+        /* route[1] = pin & 3 */
+        aml_append(while_ctx,
+            aml_store(aml_and(pin, aml_int(3)), aml_index(route, aml_int(1))));
+        /* res[pin] = route */
+        aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
+        /* pin++ */
+        aml_append(while_ctx, aml_increment(pin));
+    }
+    aml_append(method, while_ctx);
+    /* return res*/
+    aml_append(method, aml_return(res));
+
+    return method;
+}
+
 static void
 build_ssdt(GArray *table_data, GArray *linker,
            AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
@@ -655,6 +735,7 @@ build_ssdt(GArray *table_data, GArray *linker,
                        aml_name_decl("_UID", aml_string("PC%.02X", bus_num)));
             aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A03")));
             aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
+            aml_append(dev, build_prt());
             aml_append(scope, dev);
             aml_append(ssdt, scope);
         }
-- 
2.1.0

  parent reply	other threads:[~2015-06-02 11:23 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-02 11:22 [Qemu-devel] [PATCH V8 00/17] hw/pc: implement multiple primary busses for pc machines Marcel Apfelbaum
2015-06-02 11:22 ` [Qemu-devel] [PATCH V8 01/17] acpi: add implementation of aml_while() term Marcel Apfelbaum
2015-06-02 11:22 ` [Qemu-devel] [PATCH V8 02/17] hw/pci: made pci_bus_is_root a PCIBusClass method Marcel Apfelbaum
2015-06-02 11:22 ` [Qemu-devel] [PATCH V8 03/17] hw/pci: made pci_bus_num " Marcel Apfelbaum
2015-06-02 11:22 ` [Qemu-devel] [PATCH V8 04/17] hw/i386: query only for q35/pc when looking for pci host bridge Marcel Apfelbaum
2015-06-02 11:23 ` [Qemu-devel] [PATCH V8 05/17] hw/pci: extend PCI config access to support devices behind PXB Marcel Apfelbaum
2015-06-02 11:23 ` [Qemu-devel] [PATCH V8 06/17] hw/acpi: add support for i440fx 'snooping' root busses Marcel Apfelbaum
2015-06-02 11:23 ` Marcel Apfelbaum [this message]
2015-06-02 11:23 ` [Qemu-devel] [PATCH V8 08/17] hw/acpi: add _CRS method for extra " Marcel Apfelbaum
2015-06-02 11:23 ` [Qemu-devel] [PATCH V8 09/17] hw/acpi: remove from root bus 0 the crs resources used by other buses Marcel Apfelbaum
2015-06-02 11:23 ` [Qemu-devel] [PATCH V8 10/17] hw/pci: removed 'rootbus nr is 0' assumption from qmp_pci_query Marcel Apfelbaum
2015-06-02 11:23 ` [Qemu-devel] [PATCH V8 11/17] hw/pci: introduce PCI Expander Bridge (PXB) Marcel Apfelbaum
2015-06-02 11:23 ` [Qemu-devel] [PATCH V8 12/17] hw/pci: inform bios if the system has extra pci root buses Marcel Apfelbaum
2015-06-02 11:23 ` [Qemu-devel] [PATCH V8 13/17] hw/pxb: add map_irq func Marcel Apfelbaum
2015-06-02 11:23 ` [Qemu-devel] [PATCH V8 14/17] hw/pci: add support for NUMA nodes Marcel Apfelbaum
2015-06-02 11:23 ` [Qemu-devel] [PATCH V8 15/17] hw/pxb: add numa_node parameter Marcel Apfelbaum
2015-06-02 11:23 ` [Qemu-devel] [PATCH V8 16/17] apci: fix PXB behaviour if used with unsupported BIOS Marcel Apfelbaum
2015-06-02 11:23 ` [Qemu-devel] [PATCH V8 17/17] docs: Add PXB documentation Marcel Apfelbaum
2015-06-03 16:12 ` [Qemu-devel] [PATCH V8 00/17] hw/pc: implement multiple primary busses for pc machines Laszlo Ersek

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