From: Peter Zijlstra <peterz@infradead.org>
To: Scott Wood <scottwood@freescale.com>
Cc: Michael Neuling <mikey@neuling.org>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
linuxppc-dev@ozlabs.org
Subject: Re: question on FSL_EMB perf
Date: Wed, 10 Jun 2015 21:27:34 +0200 [thread overview]
Message-ID: <1433964454.1495.58.camel@twins> (raw)
In-Reply-To: <1433963830.2477.136.camel@freescale.com>
On Wed, 2015-06-10 at 14:17 -0500, Scott Wood wrote:
> On Wed, 2015-06-10 at 13:41 +0200, Peter Zijlstra wrote:
> > Hi Mike, Ben,
> >=20
> > I just noticed:
> >=20
> > arch/powerpc/Kconfig: select HAVE_PERF_EVENTS_NMI if PPC64
> >=20
> > But can't ppc32 have FSL_EMB perf?
>=20
> Yes, but it doesn't use NMIs. ppc64 has lazy interrupt disabling=20
> which functions as a pseudo-NMI.
I know. But you can get the same nesting nonsense as with actual real
NMIs.
And seeing how you select HAVE_PERF_EVENT_NMI for PPC64, I figure you
ought to select it too for whatever fsl-emb is.
# git grep nmi_enter arch/powerpc/
arch/powerpc/perf/core-book3s.c: nmi_enter();
arch/powerpc/perf/core-fsl-emb.c: nmi_enter();
next prev parent reply other threads:[~2015-06-10 19:27 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-10 11:41 question on FSL_EMB perf Peter Zijlstra
2015-06-10 19:17 ` Scott Wood
2015-06-10 19:27 ` Peter Zijlstra [this message]
2015-06-10 20:13 ` Scott Wood
2015-06-10 21:14 ` Peter Zijlstra
2015-06-10 21:28 ` Scott Wood
2015-06-11 6:00 ` Michael Ellerman
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