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From: Imre Deak <imre.deak@intel.com>
To: Damien Lespiau <damien.lespiau@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/i915: factor out intel_mode_target_cdclk
Date: Mon, 22 Jun 2015 16:46:37 +0300	[thread overview]
Message-ID: <1434980797.31905.91.camel@intel.com> (raw)
In-Reply-To: <20150622133733.GG13593@strange.amr.corp.intel.com>

On ma, 2015-06-22 at 14:37 +0100, Damien Lespiau wrote:
> On Wed, Jun 17, 2015 at 02:00:54PM +0300, Imre Deak wrote:
> > For GEN9 the target cdclk frequency is needed during the modeset state check
> > phase too, so factor out this functionality.
> > 
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> 
> I believe the "proper" way to do it is to put what you called the target
> CDCLK in the atomic state and use that here. Maarten has a patch to do
> that towards the end of his atomic series.

Yes, I was also thinking of using a pre-calculated value, but that
looked like a bigger work. I haven't seen Maarten's patch but that looks
like the way to go (Daniel also pointed to this on IRC). So I can rebase
this once Maarten's patchset lands.

--Imre

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      reply	other threads:[~2015-06-22 13:46 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-17 11:00 [PATCH 1/2] drm/i915: factor out intel_mode_target_cdclk Imre Deak
2015-06-17 11:00 ` [PATCH 2/2] drm/i915/bxt: fix max scaling factor calculation Imre Deak
2015-06-22 13:37 ` [PATCH 1/2] drm/i915: factor out intel_mode_target_cdclk Damien Lespiau
2015-06-22 13:46   ` Imre Deak [this message]

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