From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: Re: PCI Pass-through in Xen ARM - Draft 2. Date: Mon, 29 Jun 2015 11:50:09 +0100 Message-ID: <1435575009.32500.258.camel@citrix.com> References: <55903F12.7010908@caviumnetworks.com> <55911E66.2040009@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <55911E66.2040009@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Julien Grall Cc: Prasun Kapoor , "Kumar, Vijaya" , Manish Jaggi , "xen-devel@lists.xen.org" , Stefano Stabellini , "Kulkarni, Ganapatrao" List-Id: xen-devel@lists.xenproject.org On Mon, 2015-06-29 at 11:31 +0100, Julien Grall wrote: > Hi Manish, > > On 28/06/15 19:38, Manish Jaggi wrote: > > 4.1 Holes in guest memory space > > ---------------------------- > > Holes are added in the guest memory space for mapping pci device's BAR > > regions. > > These are defined in arch-arm.h > > > > /* For 32bit */ > > GUEST_MMIO_HOLE0_BASE, GUEST_MMIO_HOLE0_SIZE > > > > /* For 64bit */ > > GUEST_MMIO_HOLE1_BASE , GUEST_MMIO_HOLE1_SIZE > > The memory layout for 32bit and 64bit are exactly the same. Why do you > need to differ here? I took this to be a "hole under 4GB" and a "hole over 4GB" IOW rather than specific to 32-bit/64-bit guests it is specific to 32/64 bit devices, the latter of which could be placed higher in RAM, which is useful since the space under 4GB is naturally more limited. Ian.