From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753321AbbF3Xd6 (ORCPT ); Tue, 30 Jun 2015 19:33:58 -0400 Received: from mga02.intel.com ([134.134.136.20]:50193 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751459AbbF3Xd2 (ORCPT ); Tue, 30 Jun 2015 19:33:28 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,381,1432623600"; d="scan'208";a="516859862" From: Andi Kleen To: peterz@infradead.org Cc: linux-kernel@vger.kernel.org, Andi Kleen Subject: [PATCH 2/3] x86, perf: Use 0x11 as extra reg test value Date: Tue, 30 Jun 2015 16:33:24 -0700 Message-Id: <1435707205-6676-3-git-send-email-andi@firstfloor.org> X-Mailer: git-send-email 2.4.2 In-Reply-To: <1435707205-6676-1-git-send-email-andi@firstfloor.org> References: <1435707205-6676-1-git-send-email-andi@firstfloor.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andi Kleen The next patch adds a new perf extra reg where 0x1ff is not a valid value. Use 0x11 instead. Signed-off-by: Andi Kleen --- arch/x86/kernel/cpu/perf_event_intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 7c397e8..28b985c 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -3575,7 +3575,7 @@ __init int intel_pmu_init(void) */ if (x86_pmu.extra_regs) { for (er = x86_pmu.extra_regs; er->msr; er++) { - er->extra_msr_access = check_msr(er->msr, 0x1ffUL); + er->extra_msr_access = check_msr(er->msr, 0x11UL); /* Disable LBR select mapping */ if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access) x86_pmu.lbr_sel_map = NULL; -- 2.4.2