All of lore.kernel.org
 help / color / mirror / Atom feed
From: Tom Warren <twarren@nvidia.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] Tegra: Allow TZ writes to VPR aperature regs
Date: Wed, 29 Jul 2015 09:24:23 -0700	[thread overview]
Message-ID: <1438187063-3400-4-git-send-email-twarren@nvidia.com> (raw)
In-Reply-To: <1438187063-3400-1-git-send-email-twarren@nvidia.com>

VPR (Video Protect Region) may be reconfigured
from secure code in the kernel/OS. Set the
ALLOW_TZ_WRITE_ACCESS bit in REG_CTRL to allow
this. Also used common CONFIG option (CONFIG_LOCK_VPR)
in T124/T210 builds to enable VPR setup.

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 arch/arm/include/asm/arch-tegra124/mc.h | 2 ++
 arch/arm/include/asm/arch-tegra210/mc.h | 2 ++
 arch/arm/mach-tegra/Makefile            | 4 +---
 arch/arm/mach-tegra/vpr.c               | 9 +++++++--
 include/configs/tegra124-common.h       | 3 +++
 include/configs/tegra210-common.h       | 3 +++
 6 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/arch-tegra124/mc.h b/arch/arm/include/asm/arch-tegra124/mc.h
index 37998a4..851e3df 100644
--- a/arch/arm/include/asm/arch-tegra124/mc.h
+++ b/arch/arm/include/asm/arch-tegra124/mc.h
@@ -78,5 +78,7 @@ struct mc_ctlr {
 
 #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED		(0 << 0)
 #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED	(1 << 0)
+#define TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_DISABLED	(0 << 1)
+#define TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_ENABLED	(1 << 1)
 
 #endif	/* _TEGRA124_MC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/mc.h b/arch/arm/include/asm/arch-tegra210/mc.h
index 77e9aa5..2a20b47 100644
--- a/arch/arm/include/asm/arch-tegra210/mc.h
+++ b/arch/arm/include/asm/arch-tegra210/mc.h
@@ -68,5 +68,7 @@ struct mc_ctlr {
 
 #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED		(0 << 0)
 #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED	(1 << 0)
+#define TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_DISABLED	(0 << 1)
+#define TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_ENABLED	(1 << 1)
 
 #endif	/* _TEGRA210_MC_H_ */
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 0db8ee0..8a42216 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -24,9 +24,7 @@ obj-y += pinmux-common.o
 obj-y += powergate.o
 obj-y += xusb-padctl.o
 obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
-#TCW Fix this to use a common config switch (CONFIG_LOCK_VPR?)
-obj-$(CONFIG_TEGRA124) += vpr.o
-obj-$(CONFIG_TEGRA210) += vpr.o
+obj-$(CONFIG_LOCK_VPR) += vpr.o
 obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
 
 ifndef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-tegra/vpr.c b/arch/arm/mach-tegra/vpr.c
index f695811..091163e 100644
--- a/arch/arm/mach-tegra/vpr.c
+++ b/arch/arm/mach-tegra/vpr.c
@@ -21,14 +21,19 @@
 #include <asm/arch/tegra.h>
 #include <asm/arch/mc.h>
 
-/* Configures VPR.  Right now, all we do is turn it off. */
+/*
+ * Configures VPR. Right now, all we do is turn it off.
+ * But we set ALLOW_TZ_WRITE_ACCESS so secure code
+ * in the kernel/OS can reconfig it later if needed.
+ */
 void config_vpr(void)
 {
 	struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
 
 	/* Turn VPR off */
 	writel(0, &mc->mc_video_protect_size_mb);
-	writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
+	writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED |
+	       TEGRA_MC_VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS_ENABLED,
 	       &mc->mc_video_protect_reg_ctrl);
 	/* read back to ensure the write went through */
 	readl(&mc->mc_video_protect_reg_ctrl);
diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h
index af7698d..e850a75 100644
--- a/include/configs/tegra124-common.h
+++ b/include/configs/tegra124-common.h
@@ -70,4 +70,7 @@
 #define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
+/* Set up VPR (Video Protect Region) */
+#define CONFIG_LOCK_VPR
+
 #endif /* _TEGRA124_COMMON_H_ */
diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h
index 0348d47..267beab 100644
--- a/include/configs/tegra210-common.h
+++ b/include/configs/tegra210-common.h
@@ -73,4 +73,7 @@
 #define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
+/* Set up VPR (Video Protect Region) */
+#define CONFIG_LOCK_VPR
+
 #endif /* _TEGRA210_COMMON_H_ */
-- 
1.8.2.1.610.g562af5b

  parent reply	other threads:[~2015-07-29 16:24 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-29 16:24 [U-Boot] [PATCH] T210: P2571: Enable SD-card power via PMIC LDO2 Tom Warren
2015-07-29 16:24 ` [U-Boot] [PATCH] T210: P2571: Restore USB gadget mode (ums) Tom Warren
2015-07-29 16:24 ` [U-Boot] [PATCH] T210: P2571: Turn CPU fan on Tom Warren
2015-07-29 16:24 ` Tom Warren [this message]
2015-08-05 19:51   ` [U-Boot] [PATCH] Tegra: Allow TZ writes to VPR aperature regs Stephen Warren
2015-08-05 19:57     ` Tom Warren
2015-07-29 18:19 ` [U-Boot] [PATCH] T210: P2571: Enable SD-card power via PMIC LDO2 Stephen Warren

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1438187063-3400-4-git-send-email-twarren@nvidia.com \
    --to=twarren@nvidia.com \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.