[U-Boot] [PATCH] ddr: altera: sequencer: add RW_MGR_MEM_NUMBER_OF_RANKS

[dinguyen at opensource.altera.com <dinguyen@opensource.altera.com>]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Fix build error for socfpga_cyclone5_defconfig:

board/altera/socfpga/wrap_sdram_config.c:245:26: error: ?RW_MGR_MEM_NUMBER_OF_RANKS? undeclared here (not in a function)
make[2]: *** [spl/board/altera/socfpga/wrap_sdram_config.o] Error 1

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
Hi Marek,

This patch is based on your 02-ddr-part3 branch. It is also applicable to the
wip/boards branch as well.

Thanks,
Dinh
---
 board/altera/socfpga/qts/sequencer_defines.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/altera/socfpga/qts/sequencer_defines.h b/board/altera/socfpga/qts/sequencer_defines.h
index 32f13ac..bfe5b27 100644
--- a/board/altera/socfpga/qts/sequencer_defines.h
+++ b/board/altera/socfpga/qts/sequencer_defines.h
@@ -103,6 +103,7 @@
 #define RW_MGR_MEM_IF_READ_DQS_WIDTH 5
 #define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5
 #define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
 #define RW_MGR_MEM_ODT_WIDTH 1
 #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
 #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
-- 
2.4.5