From: <gregkh@linuxfoundation.org>
To: markos.chandras@imgtec.com, gregkh@linuxfoundation.org,
paul.burton@imgtec.com, ralf@linux-mips.org
Cc: <stable@vger.kernel.org>, <stable-commits@vger.kernel.org>
Subject: Patch "MIPS: kernel: cps-vec: Replace 'la' macro with PTR_LA" has been added to the 4.1-stable tree
Date: Thu, 06 Aug 2015 16:30:01 -0700 [thread overview]
Message-ID: <143890380122283@kroah.com> (raw)
This is a note to let you know that I've just added the patch titled
MIPS: kernel: cps-vec: Replace 'la' macro with PTR_LA
to the 4.1-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-kernel-cps-vec-replace-la-macro-with-ptr_la.patch
and it can be found in the queue-4.1 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
>From 81a02e34ded906357deac7003fbb0d36b6cc503f Mon Sep 17 00:00:00 2001
From: Markos Chandras <markos.chandras@imgtec.com>
Date: Wed, 1 Jul 2015 09:13:29 +0100
Subject: MIPS: kernel: cps-vec: Replace 'la' macro with PTR_LA
From: Markos Chandras <markos.chandras@imgtec.com>
commit 81a02e34ded906357deac7003fbb0d36b6cc503f upstream.
The PTR_LA macro will pick the correct "la" or "dla" macro to
load an address to a register. This gets rids of the following
warnings (and others) when building a 64-bit CPS kernel:
arch/mips/kernel/cps-vec.S:63: Warning: la used to load 64-bit address
arch/mips/kernel/cps-vec.S:159: Warning: la used to load 64-bit address
arch/mips/kernel/cps-vec.S:220: Warning: la used to load 64-bit address
arch/mips/kernel/cps-vec.S:240: Warning: la used to load 64-bit address
[...]
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10587/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/mips/kernel/cps-vec.S | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -60,7 +60,7 @@ LEAF(mips_cps_core_entry)
nop
/* This is an NMI */
- la k0, nmi_handler
+ PTR_LA k0, nmi_handler
jr k0
nop
@@ -156,7 +156,7 @@ dcache_done:
ehb
/* Jump to kseg0 */
- la t0, 1f
+ PTR_LA t0, 1f
jr t0
nop
@@ -217,7 +217,7 @@ LEAF(excep_intex)
.org 0x480
LEAF(excep_ejtag)
- la k0, ejtag_debug_handler
+ PTR_LA k0, ejtag_debug_handler
jr k0
nop
END(excep_ejtag)
@@ -237,7 +237,7 @@ LEAF(mips_cps_core_init)
/* ...and for the moment only 1 VPE */
dvpe
- la t1, 1f
+ PTR_LA t1, 1f
jr.hb t1
nop
@@ -298,14 +298,14 @@ LEAF(mips_cps_core_init)
LEAF(mips_cps_boot_vpes)
/* Retrieve CM base address */
- la t0, mips_cm_base
+ PTR_LA t0, mips_cm_base
lw t0, 0(t0)
/* Calculate a pointer to this cores struct core_boot_config */
lw t0, GCR_CL_ID_OFS(t0)
li t1, COREBOOTCFG_SIZE
mul t0, t0, t1
- la t1, mips_cps_core_bootcfg
+ PTR_LA t1, mips_cps_core_bootcfg
lw t1, 0(t1)
addu t0, t0, t1
@@ -351,7 +351,7 @@ LEAF(mips_cps_boot_vpes)
1: /* Enter VPE configuration state */
dvpe
- la t1, 1f
+ PTR_LA t1, 1f
jr.hb t1
nop
1: mfc0 t1, CP0_MVPCONTROL
@@ -445,7 +445,7 @@ LEAF(mips_cps_boot_vpes)
/* This VPE should be offline, halt the TC */
li t0, TCHALT_H
mtc0 t0, CP0_TCHALT
- la t0, 1f
+ PTR_LA t0, 1f
1: jr.hb t0
nop
@@ -466,10 +466,10 @@ LEAF(mips_cps_boot_vpes)
.set noat
lw $1, TI_CPU(gp)
sll $1, $1, LONGLOG
- la \dest, __per_cpu_offset
+ PTR_LA \dest, __per_cpu_offset
addu $1, $1, \dest
lw $1, 0($1)
- la \dest, cps_cpu_state
+ PTR_LA \dest, cps_cpu_state
addu \dest, \dest, $1
.set pop
.endm
Patches currently in stable-queue which might be from markos.chandras@imgtec.com are
queue-4.1/mips-kernel-cps-vec-replace-mips32r2-isa-level-with-mips64r2.patch
queue-4.1/mips-kernel-cps-vec-use-ta0-ta3-pseudo-registers-for-64-bit.patch
queue-4.1/revert-mips-kconfig-disable-smp-cps-for-64-bit.patch
queue-4.1/mips-require-o32-fp64-support-for-mips64-with-o32-compat.patch
queue-4.1/mips-fpu.h-allow-64-bit-fpu-on-a-64-bit-mips-r6-cpu.patch
queue-4.1/mips-kernel-cps-vec-replace-la-macro-with-ptr_la.patch
queue-4.1/mips-c-r4k-fix-cache-flushing-for-mt-cores.patch
queue-4.1/mips-kernel-smp-cps-fix-64-bit-compatibility-errors-due-to-pointer-casting.patch
queue-4.1/mips-kernel-cps-vec-replace-kseg0-with-ckseg0.patch
queue-4.1/mips-fix-erroneous-jr-emulation-for-mips-r6.patch
queue-4.1/mips-cps-vec-use-macros-for-various-arithmetics-and-memory-operations.patch
reply other threads:[~2015-08-06 23:30 UTC|newest]
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