[PATCH] drm/msm/mdp5: enable clocks in hw_init and set_irqmask

[Archit Taneja <architt@codeaurora.org>]

mdp5_hw_init and mdp5_set_irqmask configure registers but may not have
clocks enabled.

Add mdp5_enable/disable calls in these funcs to ensure clocks are
enabled. We need this until we get proper runtime pm support.

Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c | 10 ++++++++--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c |  2 ++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
index b1f73be..9fabfca 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
@@ -24,9 +24,15 @@
 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
 		uint32_t old_irqmask)
 {
-	mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_MDP_INTR_CLEAR(0),
+	struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
+
+	mdp5_enable(mdp5_kms);
+
+	mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_CLEAR(0),
 		irqmask ^ (irqmask & old_irqmask));
-	mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_MDP_INTR_EN(0), irqmask);
+	mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_EN(0), irqmask);
+
+	mdp5_disable(mdp5_kms);
 }
 
 static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 047cb04..2b760f5 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -32,6 +32,7 @@ static int mdp5_hw_init(struct msm_kms *kms)
 	unsigned long flags;
 
 	pm_runtime_get_sync(dev->dev);
+	mdp5_enable(mdp5_kms);
 
 	/* Magic unknown register writes:
 	 *
@@ -63,6 +64,7 @@ static int mdp5_hw_init(struct msm_kms *kms)
 
 	mdp5_ctlm_hw_reset(mdp5_kms->ctlm);
 
+	mdp5_disable(mdp5_kms);
 	pm_runtime_put_sync(dev->dev);
 
 	return 0;
-- 
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