Re: [PATCH 04/13] drm/i915/skl: Eliminate usage of pipe_wm_parameters from SKL-style WM

[Ander Conselvan De Oliveira <conselvan2@gmail.com>]

On Thu, 2015-08-20 at 18:11 -0700, Matt Roper wrote:
> Just pull the info out of the state structures rather than staging
> it in an additional set of structures.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 304 ++++++++++++++++++----------------------
>  1 file changed, 135 insertions(+), 169 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b9bcb85..0cfba0a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1779,13 +1779,6 @@ static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
>  	return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
>  }
>  
> -struct skl_pipe_wm_parameters {
> -	bool active;
> -	uint32_t pipe_htotal;
> -	uint32_t pixel_rate; /* in KHz */
> -	struct intel_plane_wm_parameters plane[I915_MAX_PLANES + 1];
> -};
> -
>  struct ilk_wm_maximums {
>  	uint16_t pri;
>  	uint16_t spr;
> @@ -2826,18 +2819,40 @@ static bool ilk_disable_lp_wm(struct drm_device *dev)
>  #define SKL_DDB_SIZE		896	/* in blocks */
>  #define BXT_DDB_SIZE		512
>  
> +/*
> + * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
> + * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES, and
> + * other universal planes are in indices 1..n.  Note that this may leave
> + * unused indices between the top "sprite" plane and the cursor.
> + */
> +static int
> +skl_wm_plane_id(const struct intel_plane *plane)
> +{
> +	switch (plane->base.type) {
> +	case DRM_PLANE_TYPE_PRIMARY:
> +		return 0;
> +	case DRM_PLANE_TYPE_CURSOR:
> +		return I915_MAX_PLANES;
> +	case DRM_PLANE_TYPE_OVERLAY:
> +		return plane->plane;
> +	default:
> +		MISSING_CASE(plane->base.type);
> +		return plane->plane;
> +	}
> +}
> +
>  static void
>  skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
>  				   struct drm_crtc *for_crtc,
>  				   const struct intel_wm_config *config,
> -				   const struct skl_pipe_wm_parameters *params,
> +				   const struct intel_crtc_state *cstate,
>  				   struct skl_ddb_entry *alloc /* out */)
>  {
>  	struct drm_crtc *crtc;
>  	unsigned int pipe_size, ddb_size;
>  	int nth_active_pipe;
>  
> -	if (!params->active) {
> +	if (!cstate->base.active) {
>  		alloc->start = 0;
>  		alloc->end = 0;
>  		return;
> @@ -2903,19 +2918,27 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
>  }
>  
>  static unsigned int
> -skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
> +skl_plane_relative_data_rate(const struct drm_plane_state *state, int y)
>  {
> +	struct intel_crtc *intel_crtc = to_intel_crtc(state->crtc);
> +	struct drm_framebuffer *fb = state->fb;
>  
>  	/* for planar format */
> -	if (p->y_bytes_per_pixel) {
> +	if (fb->pixel_format == DRM_FORMAT_NV12) {
>  		if (y)  /* y-plane data rate */
> -			return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
> +			return intel_crtc->config->pipe_src_w *
> +				intel_crtc->config->pipe_src_h *
> +				drm_format_plane_cpp(fb->pixel_format, 0);
>  		else    /* uv-plane data rate */
> -			return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
> +			return (intel_crtc->config->pipe_src_w/2) *
> +				(intel_crtc->config->pipe_src_h/2) *
> +				drm_format_plane_cpp(fb->pixel_format, 1);
>  	}
>  
>  	/* for packed formats */
> -	return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
> +	return intel_crtc->config->pipe_src_w *
> +		intel_crtc->config->pipe_src_h *
> +		fb->bits_per_pixel / 8;
>  }
>  
>  /*
> @@ -2924,23 +2947,24 @@ skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, 
> int y)
>   *   3 * 4096 * 8192  * 4 < 2^32
>   */
>  static unsigned int
> -skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
> -				 const struct skl_pipe_wm_parameters *params)
> +skl_get_total_relative_data_rate(const struct intel_crtc *intel_crtc)
>  {
> +	struct drm_device *dev = intel_crtc->base.dev;
> +	const struct intel_plane *intel_plane;
>  	unsigned int total_data_rate = 0;
> -	int plane;
>  
> -	for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
> -		const struct intel_plane_wm_parameters *p;
> +	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
> +		const struct drm_plane_state *state = intel_plane->base.state;
>  
> -		p = &params->plane[plane];
> -		if (!p->enabled)
> +		if (WARN_ON(state->fb == NULL))
>  			continue;
>  
> -		total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
> -		if (p->y_bytes_per_pixel) {
> -			total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
> -		}
> +		/* packed/uv */
> +		total_data_rate += skl_plane_relative_data_rate(state, 0);
> +
> +		if (state->fb->pixel_format == DRM_FORMAT_NV12)
> +			/* y-plane */
> +			total_data_rate += skl_plane_relative_data_rate(state, 1);
>  	}
>  
>  	return total_data_rate;
> @@ -2949,21 +2973,20 @@ skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
>  static void
>  skl_allocate_pipe_ddb(struct drm_crtc *crtc,
>  		      const struct intel_wm_config *config,
> -		      const struct skl_pipe_wm_parameters *params,
> +		      const struct intel_crtc_state *cstate,
>  		      struct skl_ddb_allocation *ddb /* out */)
>  {
>  	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	struct intel_plane *intel_plane;
>  	enum pipe pipe = intel_crtc->pipe;
>  	struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
>  	uint16_t alloc_size, start, cursor_blocks;
>  	uint16_t minimum[I915_MAX_PLANES];
>  	uint16_t y_minimum[I915_MAX_PLANES];
>  	unsigned int total_data_rate;
> -	int plane;
>  
> -	skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
> +	skl_ddb_get_pipe_allocation_limits(dev, crtc, config, cstate, alloc);
>  	alloc_size = skl_ddb_entry_size(alloc);
>  	if (alloc_size == 0) {
>  		memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
> @@ -2980,17 +3003,20 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
>  	alloc->end -= cursor_blocks;
>  
>  	/* 1. Allocate the mininum required blocks for each active plane */
> -	for_each_plane(dev_priv, pipe, plane) {
> -		const struct intel_plane_wm_parameters *p;
> +	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
> +		struct drm_plane *plane = &intel_plane->base;
> +		struct drm_framebuffer *fb = plane->fb;
> +		int id = skl_wm_plane_id(intel_plane);
>  
> -		p = &params->plane[plane];
> -		if (!p->enabled)
> +		if (fb == NULL)
> +			continue;
> +		if (plane->type == DRM_PLANE_TYPE_CURSOR)
>  			continue;
>  
> -		minimum[plane] = 8;
> -		alloc_size -= minimum[plane];
> -		y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
> -		alloc_size -= y_minimum[plane];
> +		minimum[id] = 8;
> +		alloc_size -= minimum[id];
> +		y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
> +		alloc_size -= y_minimum[id];
>  	}
>  
>  	/*
> @@ -2999,45 +3025,45 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
>  	 *
>  	 * FIXME: we may not allocate every single block here.
>  	 */
> -	total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
> +	total_data_rate = skl_get_total_relative_data_rate(intel_crtc);
>  
>  	start = alloc->start;
> -	for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
> -		const struct intel_plane_wm_parameters *p;
> +	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
> +		struct drm_plane_state *state = intel_plane->base.state;
>  		unsigned int data_rate, y_data_rate;
>  		uint16_t plane_blocks, y_plane_blocks = 0;
> +		int id = skl_wm_plane_id(intel_plane);
>  
> -		p = &params->plane[plane];
> -		if (!p->enabled)
> +		if (state->fb == NULL)
>  			continue;

Doesn't this need

	if (plane->type == DRM_PLANE_TYPE_CURSOR)
		continue;

like above?

>  
> -		data_rate = skl_plane_relative_data_rate(p, 0);
> +		data_rate = skl_plane_relative_data_rate(state, 0);
>  
>  		/*
>  		 * allocation for (packed formats) or (uv-plane part of planar format):
>  		 * promote the expression to 64 bits to avoid overflowing, the
>  		 * result is < available as data_rate / total_data_rate < 1
>  		 */
> -		plane_blocks = minimum[plane];
> +		plane_blocks = minimum[id];
>  		plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
>  					total_data_rate);
>  
> -		ddb->plane[pipe][plane].start = start;
> -		ddb->plane[pipe][plane].end = start + plane_blocks;
> +		ddb->plane[pipe][id].start = start;
> +		ddb->plane[pipe][id].end = start + plane_blocks;
>  
>  		start += plane_blocks;
>  
>  		/*
>  		 * allocation for y_plane part of planar format:
>  		 */
> -		if (p->y_bytes_per_pixel) {
> -			y_data_rate = skl_plane_relative_data_rate(p, 1);
> -			y_plane_blocks = y_minimum[plane];
> +		if (state->fb->pixel_format == DRM_FORMAT_NV12) {
> +			y_data_rate = skl_plane_relative_data_rate(state, 1);
> +			y_plane_blocks = y_minimum[id];
>  			y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
>  						total_data_rate);
>  
> -			ddb->y_plane[pipe][plane].start = start;
> -			ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
> +			ddb->y_plane[pipe][id].start = start;
> +			ddb->y_plane[pipe][id].end = start + y_plane_blocks;
>  
>  			start += y_plane_blocks;
>  		}
> @@ -3138,72 +3164,16 @@ static void skl_compute_wm_global_parameters(struct drm_device *dev,
>  	}
>  }
>  
> -static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
> -					   struct skl_pipe_wm_parameters *p)
> -{
> -	struct drm_device *dev = crtc->dev;
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	enum pipe pipe = intel_crtc->pipe;
> -	struct drm_plane *plane;
> -	struct drm_framebuffer *fb;
> -	int i = 1; /* Index for sprite planes start */
> -
> -	p->active = intel_crtc->active;
> -	if (p->active) {
> -		p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
> -		p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
> -
> -		fb = crtc->primary->state->fb;
> -		/* For planar: Bpp is for uv plane, y_Bpp is for y plane */
> -		if (fb) {
> -			p->plane[0].enabled = true;
> -			p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
> -				drm_format_plane_cpp(fb->pixel_format, 1) : fb->bits_per_pixel / 
> 8;
> -			p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
> -				drm_format_plane_cpp(fb->pixel_format, 0) : 0;
> -			p->plane[0].tiling = fb->modifier[0];
> -		} else {
> -			p->plane[0].enabled = false;
> -			p->plane[0].bytes_per_pixel = 0;
> -			p->plane[0].y_bytes_per_pixel = 0;
> -			p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
> -		}
> -		p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
> -		p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
> -		p->plane[0].rotation = crtc->primary->state->rotation;
> -
> -		fb = crtc->cursor->state->fb;
> -		p->plane[I915_MAX_PLANES].y_bytes_per_pixel = 0;
> -		if (fb) {
> -			p->plane[I915_MAX_PLANES].enabled = true;
> -			p->plane[I915_MAX_PLANES].bytes_per_pixel = fb->bits_per_pixel / 8;
> -			p->plane[I915_MAX_PLANES].horiz_pixels = crtc->cursor->state->crtc_w;
> -			p->plane[I915_MAX_PLANES].vert_pixels = crtc->cursor->state->crtc_h;
> -		} else {
> -			p->plane[I915_MAX_PLANES].enabled = false;
> -			p->plane[I915_MAX_PLANES].bytes_per_pixel = 0;
> -			p->plane[I915_MAX_PLANES].horiz_pixels = 64;
> -			p->plane[I915_MAX_PLANES].vert_pixels = 64;
> -		}
> -	}
> -
> -	list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
> -		struct intel_plane *intel_plane = to_intel_plane(plane);
> -
> -		if (intel_plane->pipe == pipe &&
> -			plane->type == DRM_PLANE_TYPE_OVERLAY)
> -			p->plane[i++] = intel_plane->wm;
> -	}
> -}
> -
>  static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> -				 struct skl_pipe_wm_parameters *p,
> -				 struct intel_plane_wm_parameters *p_params,
> +				 struct intel_crtc *intel_crtc,
> +				 struct intel_plane *intel_plane,
>  				 uint16_t ddb_allocation,
>  				 int level,
>  				 uint16_t *out_blocks, /* out */
>  				 uint8_t *out_lines /* out */)
>  {
> +	struct drm_plane *plane = &intel_plane->base;
> +	struct drm_framebuffer *fb = plane->state->fb;
>  	uint32_t latency = dev_priv->wm.skl_latency[level];
>  	uint32_t method1, method2;
>  	uint32_t plane_bytes_per_line, plane_blocks_per_line;
> @@ -3211,31 +3181,35 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>  	uint32_t selected_result;
>  	uint8_t bytes_per_pixel;
>  
> -	if (latency == 0 || !p->active || !p_params->enabled)
> +	if (latency == 0 || !intel_crtc->active || !fb)

In other places you replaced p->actice with cstate->active. Is there a reason why this one doesn't
look at the state? 

>  		return false;
>  
> -	bytes_per_pixel = p_params->y_bytes_per_pixel ?
> -		p_params->y_bytes_per_pixel :
> -		p_params->bytes_per_pixel;
> -	method1 = skl_wm_method1(p->pixel_rate,
> +	bytes_per_pixel = (fb->pixel_format == DRM_FORMAT_NV12) ?
> +		drm_format_plane_cpp(DRM_FORMAT_NV12, 0) :
> +		fb->bits_per_pixel / 8;
> +	method1 = skl_wm_method1(skl_pipe_pixel_rate(intel_crtc->config),
>  				 bytes_per_pixel,
>  				 latency);
> -	method2 = skl_wm_method2(p->pixel_rate,
> -				 p->pipe_htotal,
> -				 p_params->horiz_pixels,
> +	method2 = skl_wm_method2(skl_pipe_pixel_rate(intel_crtc->config),
> +				 intel_crtc->config->base.adjusted_mode.crtc_htotal,
> +				 intel_crtc->config->pipe_src_w,

The other functions were changed to receive the crtc state as an argument. Maybe it would be good to
do that here too for consistency.

Ander

>  				 bytes_per_pixel,
> -				 p_params->tiling,
> +				 fb->modifier[0],
>  				 latency);
>  
> -	plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
> +	plane_bytes_per_line = intel_crtc->config->pipe_src_w * bytes_per_pixel;
>  	plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
>  
> -	if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
> -	    p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
> +	if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
> +	    fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
>  		uint32_t min_scanlines = 4;
>  		uint32_t y_tile_minimum;
> -		if (intel_rotation_90_or_270(p_params->rotation)) {
> -			switch (p_params->bytes_per_pixel) {
> +		if (intel_rotation_90_or_270(plane->state->rotation)) {
> +			int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
> +				drm_format_plane_cpp(fb->pixel_format, 1) :
> +				fb->bits_per_pixel / 8;
> +
> +			switch (bpp) {
>  			case 1:
>  				min_scanlines = 16;
>  				break;
> @@ -3259,8 +3233,8 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>  	res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
>  
>  	if (level >= 1 && level <= 7) {
> -		if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
> -		    p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
> +		if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
> +		    fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
>  			res_lines += 4;
>  		else
>  			res_blocks++;
> @@ -3277,65 +3251,64 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>  
>  static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
>  				 struct skl_ddb_allocation *ddb,
> -				 struct skl_pipe_wm_parameters *p,
> -				 enum pipe pipe,
> +				 struct intel_crtc *intel_crtc,
>  				 int level,
> -				 int num_planes,
>  				 struct skl_wm_level *result)
>  {
> +	struct drm_device *dev = intel_crtc->base.dev;
> +	struct intel_plane *intel_plane;
>  	uint16_t ddb_blocks;
> -	int i;
> +	enum pipe pipe = intel_crtc->pipe;
> +
> +	for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
> +		int i = skl_wm_plane_id(intel_plane);
>  
> -	for (i = 0; i < num_planes; i++) {
>  		ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
>  
>  		result->plane_en[i] = skl_compute_plane_wm(dev_priv,
> -						p, &p->plane[i],
> +						intel_crtc,
> +						intel_plane,
>  						ddb_blocks,
>  						level,
>  						&result->plane_res_b[i],
>  						&result->plane_res_l[i]);
>  	}
> -
> -	ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][I915_MAX_PLANES]);
> -	result->plane_en[I915_MAX_PLANES] = skl_compute_plane_wm(dev_priv, p,
> -						 &p->plane[I915_MAX_PLANES],
> -						 ddb_blocks, level,
> -						 &result->plane_res_b[I915_MAX_PLANES],
> -						 &result->plane_res_l[I915_MAX_PLANES]);
>  }
>  
>  static uint32_t
> -skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
> +skl_compute_linetime_wm(struct intel_crtc_state *cstate)
>  {
> -	if (!to_intel_crtc(crtc)->active)
> +	if (!cstate->base.active)
>  		return 0;
>  
> -	if (WARN_ON(p->pixel_rate == 0))
> +	if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
>  		return 0;
>  
> -	return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
> +	return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
> +			    skl_pipe_pixel_rate(cstate));
>  }
>  
> -static void skl_compute_transition_wm(struct drm_crtc *crtc,
> -				      struct skl_pipe_wm_parameters *params,
> +static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
>  				      struct skl_wm_level *trans_wm /* out */)
>  {
> +	struct drm_crtc *crtc = cstate->base.crtc;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	int i;
> +	struct intel_plane *intel_plane;
>  
> -	if (!params->active)
> +	if (!cstate->base.active)
>  		return;
>  
>  	/* Until we know more, just disable transition WMs */
> -	for (i = 0; i < intel_num_planes(intel_crtc); i++)
> +	for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
> +		int i = skl_wm_plane_id(intel_plane);
> +
>  		trans_wm->plane_en[i] = false;
> -	trans_wm->plane_en[I915_MAX_PLANES] = false;
> +	}
>  }
>  
>  static void skl_compute_pipe_wm(struct drm_crtc *crtc,
>  				struct skl_ddb_allocation *ddb,
> -				struct skl_pipe_wm_parameters *params,
> +				struct intel_crtc_state *cstate,
>  				struct skl_pipe_wm *pipe_wm)
>  {
>  	struct drm_device *dev = crtc->dev;
> @@ -3344,17 +3317,15 @@ static void skl_compute_pipe_wm(struct drm_crtc *crtc,
>  	int level, max_level = ilk_wm_max_level(dev);
>  
>  	for (level = 0; level <= max_level; level++) {
> -		skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
> -				     level, intel_num_planes(intel_crtc),
> -				     &pipe_wm->wm[level]);
> +		skl_compute_wm_level(dev_priv, ddb, intel_crtc,
> +				     level, &pipe_wm->wm[level]);
>  	}
> -	pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
> +	pipe_wm->linetime = skl_compute_linetime_wm(cstate);
>  
> -	skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
> +	skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
>  }
>  
>  static void skl_compute_wm_results(struct drm_device *dev,
> -				   struct skl_pipe_wm_parameters *p,
>  				   struct skl_pipe_wm *p_wm,
>  				   struct skl_wm_values *r,
>  				   struct intel_crtc *intel_crtc)
> @@ -3598,16 +3569,15 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
>  }
>  
>  static bool skl_update_pipe_wm(struct drm_crtc *crtc,
> -			       struct skl_pipe_wm_parameters *params,
>  			       struct intel_wm_config *config,
>  			       struct skl_ddb_allocation *ddb, /* out */
>  			       struct skl_pipe_wm *pipe_wm /* out */)
>  {
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
>  
> -	skl_compute_wm_pipe_parameters(crtc, params);
> -	skl_allocate_pipe_ddb(crtc, config, params, ddb);
> -	skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
> +	skl_allocate_pipe_ddb(crtc, config, cstate, ddb);
> +	skl_compute_pipe_wm(crtc, ddb, cstate, pipe_wm);
>  
>  	if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
>  		return false;
> @@ -3640,7 +3610,6 @@ static void skl_update_other_pipe_wm(struct drm_device *dev,
>  	 */
>  	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
>  				base.head) {
> -		struct skl_pipe_wm_parameters params = {};
>  		struct skl_pipe_wm pipe_wm = {};
>  		bool wm_changed;
>  
> @@ -3650,8 +3619,7 @@ static void skl_update_other_pipe_wm(struct drm_device *dev,
>  		if (!intel_crtc->active)
>  			continue;
>  
> -		wm_changed = skl_update_pipe_wm(&intel_crtc->base,
> -						&params, config,
> +		wm_changed = skl_update_pipe_wm(&intel_crtc->base, config,
>  						&r->ddb, &pipe_wm);
>  
>  		/*
> @@ -3661,7 +3629,7 @@ static void skl_update_other_pipe_wm(struct drm_device *dev,
>  		 */
>  		WARN_ON(!wm_changed);
>  
> -		skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
> +		skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
>  		r->dirty[intel_crtc->pipe] = true;
>  	}
>  }
> @@ -3671,7 +3639,6 @@ static void skl_update_wm(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct skl_pipe_wm_parameters params = {};
>  	struct skl_wm_values *results = &dev_priv->wm.skl_results;
>  	struct skl_pipe_wm pipe_wm = {};
>  	struct intel_wm_config config = {};
> @@ -3680,11 +3647,10 @@ static void skl_update_wm(struct drm_crtc *crtc)
>  
>  	skl_compute_wm_global_parameters(dev, &config);
>  
> -	if (!skl_update_pipe_wm(crtc, &params, &config,
> -				&results->ddb, &pipe_wm))
> +	if (!skl_update_pipe_wm(crtc, &config, &results->ddb, &pipe_wm))
>  		return;
>  
> -	skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
> +	skl_compute_wm_results(dev, &pipe_wm, results, intel_crtc);
>  	results->dirty[intel_crtc->pipe] = true;
>  
>  	skl_update_other_pipe_wm(dev, crtc, &config, results);
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