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From: Deepak M <m.deepak@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Deepak M <m.deepak@intel.com>
Subject: [MIPI SEQ PARSING v2 PATCH 06/11] drm/i915: extending gpio read/write to other cores
Date: Thu, 10 Sep 2015 04:54:25 +0530	[thread overview]
Message-ID: <1441841070-11532-7-git-send-email-m.deepak@intel.com> (raw)
In-Reply-To: <1441841070-11532-1-git-send-email-m.deepak@intel.com>

Adding a argument to the gpio read/write functions
which accepts the block name.

v2: rebase

Signed-off-by: Deepak M <m.deepak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h            |    5 +++--
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |    4 ++--
 drivers/gpu/drm/i915/intel_sideband.c      |    9 +++++----
 3 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 91ccbc6..ed3b19b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3363,8 +3363,9 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val
 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
-u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
-void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 vlv_gpio_read(struct drm_i915_private *dev_priv, u8 core_offset, u32 reg);
+void vlv_gpio_write(struct drm_i915_private *dev_priv, u8 core_offset,
+			u32 reg, u32 val);
 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index c6a6fa1..02f1cd5 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -276,14 +276,14 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 	if (!gtable[gpio].init) {
 		/* program the function */
 		/* FIXME: remove constant below */
-		vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
+		vlv_gpio_write(dev_priv, IOSF_PORT_GPIO_NC, function, 0x2000CC00);
 		gtable[gpio].init = 1;
 	}
 
 	val = 0x4 | action;
 
 	/* pull up/down */
-	vlv_gpio_nc_write(dev_priv, pad, val);
+	vlv_gpio_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
 	mutex_unlock(&dev_priv->sb_lock);
 
 	return data;
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 8831fc5..3e0cbe6 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -129,17 +129,18 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
 	return val;
 }
 
-u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
+u32 vlv_gpio_read(struct drm_i915_private *dev_priv, u8 core_offset, u32 reg)
 {
 	u32 val = 0;
-	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
+	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), core_offset,
 			SB_CRRDDA_NP, reg, &val);
 	return val;
 }
 
-void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+void vlv_gpio_write(struct drm_i915_private *dev_priv, u8 core_offset,
+				u32 reg, u32 val)
 {
-	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
+	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), core_offset,
 			SB_CRWRDA_NP, reg, &val);
 }
 
-- 
1.7.9.5

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  parent reply	other threads:[~2015-09-09 23:20 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-09 23:24 [MIPI SEQ PARSING v2 PATCH 00/11] Patches to support the version 3 of MIPI sequence in VBT Deepak M
2015-09-09 23:24 ` [MIPI SEQ PARSING v2 PATCH 01/11] drm/i915: Adding the parsing logic for the i2c element Deepak M
2015-09-17  9:18   ` Jani Nikula
2015-09-22  6:46     ` Deepak, M
2015-09-09 23:24 ` [MIPI SEQ PARSING v2 PATCH 02/11] drm/i915: Updating asle structure with new fields Deepak M
2015-09-09 23:24 ` [MIPI SEQ PARSING v2 PATCH 03/11] drm/i915: Parsing VBT if size of VBT exceeds 6KB Deepak M
2015-09-16 13:24   ` Jani Nikula
2015-09-17 12:10   ` Jani Nikula
2015-09-22  6:37     ` Deepak, M
2015-09-22  7:24       ` Jani Nikula
2015-09-09 23:24 ` [MIPI SEQ PARSING v2 PATCH 04/11] drm/i915: Using the approprite vbt size if vbt is not in mailbox4 of opregion Deepak M
2015-09-17 12:18   ` Jani Nikula
2015-09-17 13:31     ` Jani Nikula
2015-09-22  6:11       ` Deepak, M
2015-09-22  6:24     ` Deepak, M
2015-09-09 23:24 ` [MIPI SEQ PARSING v2 PATCH 05/11] drm/i915: Added support the v3 mipi sequence block Deepak M
2015-09-17 14:38   ` Jani Nikula
2015-09-22  6:23     ` Deepak, M
2015-09-09 23:24 ` Deepak M [this message]
2015-09-09 23:24 ` [MIPI SEQ PARSING v2 PATCH 07/11] drm/i915: Added the generic gpio sequence support and gpio table Deepak M
2015-09-17 14:44   ` Jani Nikula
2015-09-09 23:24 ` [MIPI SEQ PARSING v2 PATCH 08/11] drm/i915: GPIO for CHT generic MIPI Deepak M
2015-09-09 23:24 ` [MIPI SEQ PARSING v2 PATCH 09/11] drm: Add few more wrapper functions for drm panel Deepak M
2015-09-09 23:24 ` [MIPI SEQ PARSING v2 PATCH 10/11] drm/i915: Add functions to execute the new sequences from VBT Deepak M
2015-09-09 23:24 ` [MIPI SEQ PARSING v2 PATCH 11/11] drm/i915: BXT GPIO support for backlight and panel control Deepak M

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