From mboxrd@z Thu Jan 1 00:00:00 1970 From: Hai Li Subject: [PATCH] drm/msm/dsi: Updata LNn_CFG4 register settings for 28nm PHY Date: Fri, 11 Sep 2015 15:56:09 -0400 Message-ID: <1442001369-12043-1-git-send-email-hali@codeaurora.org> References: <1442000412-8790-1-git-send-email-hali@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1442000412-8790-1-git-send-email-hali@codeaurora.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org VGhlIGN1cnJlbnQgc2V0dGluZ3MgZm9yIDI4bm0gUEhZIGRhdGEgbGFuZSBDRkc0IHJlZ2lzdGVy cyBkbwpub3Qgd29yayB3aXRoIGNlcnRhaW4gcGFuZWxzLiBUaGlzIGNoYW5nZSBpcyB0byBtb2Rp ZnkgdGhlbSB0bwpodyByZWNvbW1lbmRlZCB2YWx1ZXMuCgpTaWduZWQtb2ZmLWJ5OiBIYWkgTGkg PGhhbGlAY29kZWF1cm9yYS5vcmc+Ci0tLQogZHJpdmVycy9ncHUvZHJtL21zbS9kc2kvcGh5L2Rz aV9waHlfMjhubS5jIHwgNiArKy0tLS0KIDEgZmlsZSBjaGFuZ2VkLCAyIGluc2VydGlvbnMoKyks IDQgZGVsZXRpb25zKC0pCgpkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21zbS9kc2kvcGh5 L2RzaV9waHlfMjhubS5jIGIvZHJpdmVycy9ncHUvZHJtL21zbS9kc2kvcGh5L2RzaV9waHlfMjhu bS5jCmluZGV4IGYxYTdjN2IuLmVkZjc0MTEgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9t c20vZHNpL3BoeS9kc2lfcGh5XzI4bm0uYworKysgYi9kcml2ZXJzL2dwdS9kcm0vbXNtL2RzaS9w aHkvZHNpX3BoeV8yOG5tLmMKQEAgLTk5LDE2ICs5OSwxNCBAQCBzdGF0aWMgaW50IGRzaV8yOG5t X3BoeV9lbmFibGUoc3RydWN0IG1zbV9kc2lfcGh5ICpwaHksIGludCBzcmNfcGxsX2lkLAogCQlk c2lfcGh5X3dyaXRlKGJhc2UgKyBSRUdfRFNJXzI4bm1fUEhZX0xOX0NGR18xKGkpLCAwKTsKIAkJ ZHNpX3BoeV93cml0ZShiYXNlICsgUkVHX0RTSV8yOG5tX1BIWV9MTl9DRkdfMihpKSwgMCk7CiAJ CWRzaV9waHlfd3JpdGUoYmFzZSArIFJFR19EU0lfMjhubV9QSFlfTE5fQ0ZHXzMoaSksIDApOwor CQlkc2lfcGh5X3dyaXRlKGJhc2UgKyBSRUdfRFNJXzI4bm1fUEhZX0xOX0NGR180KGkpLCAwKTsK IAkJZHNpX3BoeV93cml0ZShiYXNlICsgUkVHX0RTSV8yOG5tX1BIWV9MTl9URVNUX0RBVEFQQVRI KGkpLCAwKTsKIAkJZHNpX3BoeV93cml0ZShiYXNlICsgUkVHX0RTSV8yOG5tX1BIWV9MTl9ERUJV R19TRUwoaSksIDApOwogCQlkc2lfcGh5X3dyaXRlKGJhc2UgKyBSRUdfRFNJXzI4bm1fUEhZX0xO X1RFU1RfU1RSXzAoaSksIDB4MSk7CiAJCWRzaV9waHlfd3JpdGUoYmFzZSArIFJFR19EU0lfMjhu bV9QSFlfTE5fVEVTVF9TVFJfMShpKSwgMHg5Nyk7CiAJfQotCWRzaV9waHlfd3JpdGUoYmFzZSAr IFJFR19EU0lfMjhubV9QSFlfTE5fQ0ZHXzQoMCksIDApOwotCWRzaV9waHlfd3JpdGUoYmFzZSAr IFJFR19EU0lfMjhubV9QSFlfTE5fQ0ZHXzQoMSksIDB4NSk7Ci0JZHNpX3BoeV93cml0ZShiYXNl ICsgUkVHX0RTSV8yOG5tX1BIWV9MTl9DRkdfNCgyKSwgMHhhKTsKLQlkc2lfcGh5X3dyaXRlKGJh c2UgKyBSRUdfRFNJXzI4bm1fUEhZX0xOX0NGR180KDMpLCAweGYpOwogCisJZHNpX3BoeV93cml0 ZShiYXNlICsgUkVHX0RTSV8yOG5tX1BIWV9MTkNLX0NGR180LCAwKTsKIAlkc2lfcGh5X3dyaXRl KGJhc2UgKyBSRUdfRFNJXzI4bm1fUEhZX0xOQ0tfQ0ZHXzEsIDB4YzApOwogCWRzaV9waHlfd3Jp dGUoYmFzZSArIFJFR19EU0lfMjhubV9QSFlfTE5DS19URVNUX1NUUjAsIDB4MSk7CiAJZHNpX3Bo eV93cml0ZShiYXNlICsgUkVHX0RTSV8yOG5tX1BIWV9MTkNLX1RFU1RfU1RSMSwgMHhiYik7Ci0t IApUaGUgUXVhbGNvbW0gSW5ub3ZhdGlvbiBDZW50ZXIsIEluYy4gaXMgYSBtZW1iZXIgb2YgdGhl IENvZGUgQXVyb3JhIEZvcnVtLApob3N0ZWQgYnkgVGhlIExpbnV4IEZvdW5kYXRpb24KCl9fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWls aW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwOi8vbGlzdHMuZnJl ZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753913AbbIKT5U (ORCPT ); Fri, 11 Sep 2015 15:57:20 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:58926 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753804AbbIKT5Q (ORCPT ); Fri, 11 Sep 2015 15:57:16 -0400 From: Hai Li To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, robdclark@gmail.com, Hai Li Subject: [PATCH] drm/msm/dsi: Updata LNn_CFG4 register settings for 28nm PHY Date: Fri, 11 Sep 2015 15:56:09 -0400 Message-Id: <1442001369-12043-1-git-send-email-hali@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1442000412-8790-1-git-send-email-hali@codeaurora.org> References: <1442000412-8790-1-git-send-email-hali@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current settings for 28nm PHY data lane CFG4 registers do not work with certain panels. This change is to modify them to hw recommended values. Signed-off-by: Hai Li --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index f1a7c7b..edf7411 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -99,16 +99,14 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_1(i), 0); dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_2(i), 0); dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_3(i), 0); + dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(i), 0); dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i), 0); dsi_phy_write(base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i), 0); dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i), 0x1); dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i), 0x97); } - dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(0), 0); - dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(1), 0x5); - dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(2), 0xa); - dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(3), 0xf); + dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_4, 0); dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_1, 0xc0); dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR0, 0x1); dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR1, 0xbb); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation