Re: [PATCH] KVM: PPC: e6500: support powers of 2K TLB1 sizes

[Scott Wood <scottwood@freescale.com>]

On Fri, 2015-09-25 at 17:30 +0300, Laurentiu Tudor wrote:
> On 09/24/2015 11:23 PM, Scott Wood wrote:
> > On Thu, 2015-09-24 at 15:57 +0300, Laurentiu Tudor wrote:
> > > Book-E MMUv2 present in e6500 cores supports
> > > powers of 2K page sizes while older MMUv1 cores
> > > support only powers of 4K page sizes, or in other
> > > words the LSB of TSIZE on MMUv1 is always 0.
> > > Thus, on MMUv2 we must not strip the LSB.
> > 
> > We can get better TLB utilization by not stripping it, but why "must not" 
> > which makes it sound like a bugfix rather than an optimization?
> 
> Not sure i get it. If a guests wants a 2K^^(2n+1) translation
> size it will instead get a 2K^^2n size, no? Isn't this an issue?

It will get two pages of 2k^^2n size (assuming both halves are accessed).  It 
will work, it will just consume twice as many TLB1 entries.  It's the same as 
if the host pages backing the region are smaller than the mapping that the 
guest tries to create.

-Scott