Re: [PATCH 2/3] drm/i915/bxt: add revision id for A1 stepping and use it

["Vivi, Rodrigo" <rodrigo.vivi@intel.com>]

On Tue, 2015-10-06 at 16:43 +0300, Jani Nikula wrote:
> On Tue, 06 Oct 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> 
> wrote:
> > On Tue, Oct 06, 2015 at 02:41:15PM +0300, Jani Nikula wrote:
> > > Prefer inclusive ranges for revision checks rather than "below 
> > > B0". Per
> > > specs A2 is not used, so revid <= A1 matches revid < B0.
> > 
> > The w/a db would say UNTIL_B0 etc., so might be easier to check 
> > against
> > it if we keep to the same convention.
> 
> So I wanted to double check what the convention is. I picked
> WaRsDisableCoarsePowerGating.
> 
> KBL - SIWA_FOREVER
> BXT - SI_WA_BEFORE(BXT_REV_ID_B0)
> SKL - SIWA_UNTIL_SKL_E0
> 
> Description "Disable coarse power gating for GT4 until GT F0 
> stepping."
> 
> *rolls eyes*
> 
> So is that "until" there inclusive or non-inclusive? The db is
> contradicting itself... Cc: Sarah who has also looked at workarounds
> recently.
> 
> Rodrigo, for one thing, I'll want workarounds for SKL and KBL in
> different conditions instead of conflated into SKL!

I agree with Ville that <= REVID matches the spec in sense of "until"
certain stepping and I like this.

Also KBL W/A doesn't conflict with SKL W/as in they way they were
derivated...

> 
> But what about this non-inclusive end of range? It'll matter in patch
> 3/3. It's not so much a problem for ranges, but rather for specific
> revisions, where you'd have to include a revision not mentioned in 
> the
> spec at all, e.g. for B0 only:
> 
> 	IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_C0)
> 
> instead of the current proposal:
> 
> 	IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0)
> 
> I'm not really fond of adding separate macros for checking specific
> vs. ranges.
> 
> Thoughts?
> 
> BR,
> Jani.
> 
> 
> 
> 
> 
> > 
> > > 
> > > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_drv.h            | 1 +
> > >  drivers/gpu/drm/i915/i915_gem.c            | 2 +-
> > >  drivers/gpu/drm/i915/i915_guc_submission.c | 2 +-
> > >  drivers/gpu/drm/i915/intel_ddi.c           | 2 +-
> > >  drivers/gpu/drm/i915/intel_dp.c            | 2 +-
> > >  drivers/gpu/drm/i915/intel_hdmi.c          | 2 +-
> > >  drivers/gpu/drm/i915/intel_lrc.c           | 8 ++++----
> > >  drivers/gpu/drm/i915/intel_pm.c            | 6 +++---
> > >  drivers/gpu/drm/i915/intel_ringbuffer.c    | 6 +++---
> > >  9 files changed, 16 insertions(+), 15 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > index a3b137715604..9833a2055930 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -2509,6 +2509,7 @@ struct drm_i915_cmd_table {
> > >  #define SKL_REVID_F0		0x5
> > >  
> > >  #define BXT_REVID_A0		0x0
> > > +#define BXT_REVID_A1		0x1
> > >  #define BXT_REVID_B0		0x3
> > >  #define BXT_REVID_C0		0x9
> > >  
> > > diff --git a/drivers/gpu/drm/i915/i915_gem.c 
> > > b/drivers/gpu/drm/i915/i915_gem.c
> > > index f0cfbb9ee12c..fd2d880656b2 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > > @@ -3757,7 +3757,7 @@ int i915_gem_set_caching_ioctl(struct 
> > > drm_device *dev, void *data,
> > >  		 * cacheline, whereas normally such cachelines 
> > > would get
> > >  		 * invalidated.
> > >  		 */
> > > -		if (IS_BROXTON(dev) && INTEL_REVID(dev) < 
> > > BXT_REVID_B0)
> > > +		if (IS_BROXTON(dev) && INTEL_REVID(dev) <= 
> > > BXT_REVID_A1)
> > >  			return -ENODEV;
> > >  
> > >  		level = I915_CACHE_LLC;
> > > diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
> > > b/drivers/gpu/drm/i915/i915_guc_submission.c
> > > index 036b42bae827..863aa5c82466 100644
> > > --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> > > +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> > > @@ -161,7 +161,7 @@ static int host2guc_sample_forcewake(struct 
> > > intel_guc *guc,
> > >  	data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
> > >  	/* WaRsDisableCoarsePowerGating:skl,bxt */
> > >  	if (!intel_enable_rc6(dev_priv->dev) ||
> > > -	    (IS_BROXTON(dev) && (INTEL_REVID(dev) < 
> > > BXT_REVID_B0)) ||
> > > +	    (IS_BROXTON(dev) && (INTEL_REVID(dev) <= 
> > > BXT_REVID_A1)) ||
> > >  	    (IS_SKL_GT3(dev) && (INTEL_REVID(dev) <= 
> > > SKL_REVID_E0)) ||
> > >  	    (IS_SKL_GT4(dev) && (INTEL_REVID(dev) <= 
> > > SKL_REVID_E0)))
> > >  		data[1] = 0;
> > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> > > b/drivers/gpu/drm/i915/intel_ddi.c
> > > index b25e99a432fb..b80e0f5ec5dc 100644
> > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > @@ -3247,7 +3247,7 @@ void intel_ddi_init(struct drm_device *dev, 
> > > enum port port)
> > >  		 * On BXT A0/A1, sw needs to activate DDIA HPD 
> > > logic and
> > >  		 * interrupts to check the external panel 
> > > connection.
> > >  		 */
> > > -		if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < 
> > > BXT_REVID_B0)
> > > +		if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= 
> > > BXT_REVID_A1)
> > >  					 && port == PORT_B)
> > >  			dev_priv->hotplug.irq_port[PORT_A] = 
> > > intel_dig_port;
> > >  		else
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index 8d34ca7b287a..8baf6fe06313 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -6087,7 +6087,7 @@ intel_dp_init_connector(struct 
> > > intel_digital_port *intel_dig_port,
> > >  		break;
> > >  	case PORT_B:
> > >  		intel_encoder->hpd_pin = HPD_PORT_B;
> > > -		if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < 
> > > BXT_REVID_B0))
> > > +		if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= 
> > > BXT_REVID_A1))
> > >  			intel_encoder->hpd_pin = HPD_PORT_A;
> > >  		break;
> > >  	case PORT_C:
> > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
> > > b/drivers/gpu/drm/i915/intel_hdmi.c
> > > index 03d85909c6ab..32e9117ee8e3 100644
> > > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > > @@ -2068,7 +2068,7 @@ void intel_hdmi_init_connector(struct 
> > > intel_digital_port *intel_dig_port,
> > >  		 * On BXT A0/A1, sw needs to activate DDIA HPD 
> > > logic and
> > >  		 * interrupts to check the external panel 
> > > connection.
> > >  		 */
> > > -		if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < 
> > > BXT_REVID_B0))
> > > +		if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= 
> > > BXT_REVID_A1))
> > >  			intel_encoder->hpd_pin = HPD_PORT_A;
> > >  		else
> > >  			intel_encoder->hpd_pin = HPD_PORT_B;
> > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> > > b/drivers/gpu/drm/i915/intel_lrc.c
> > > index 825fa7a8df86..acd4fa332a80 100644
> > > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > > @@ -1986,7 +1986,7 @@ static int logical_render_ring_init(struct 
> > > drm_device *dev)
> > >  		ring->init_hw = gen8_init_render_ring;
> > >  	ring->init_context = gen8_init_rcs_context;
> > >  	ring->cleanup = intel_fini_pipe_control;
> > > -	if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) 
> > > {
> > > +	if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) 
> > > {
> > >  		ring->get_seqno = bxt_a_get_seqno;
> > >  		ring->set_seqno = bxt_a_set_seqno;
> > >  	} else {
> > > @@ -2038,7 +2038,7 @@ static int logical_bsd_ring_init(struct 
> > > drm_device *dev)
> > >  		GT_CONTEXT_SWITCH_INTERRUPT << 
> > > GEN8_VCS1_IRQ_SHIFT;
> > >  
> > >  	ring->init_hw = gen8_init_common_ring;
> > > -	if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) 
> > > {
> > > +	if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) 
> > > {
> > >  		ring->get_seqno = bxt_a_get_seqno;
> > >  		ring->set_seqno = bxt_a_set_seqno;
> > >  	} else {
> > > @@ -2093,7 +2093,7 @@ static int logical_blt_ring_init(struct 
> > > drm_device *dev)
> > >  		GT_CONTEXT_SWITCH_INTERRUPT << 
> > > GEN8_BCS_IRQ_SHIFT;
> > >  
> > >  	ring->init_hw = gen8_init_common_ring;
> > > -	if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) 
> > > {
> > > +	if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) 
> > > {
> > >  		ring->get_seqno = bxt_a_get_seqno;
> > >  		ring->set_seqno = bxt_a_set_seqno;
> > >  	} else {
> > > @@ -2123,7 +2123,7 @@ static int logical_vebox_ring_init(struct 
> > > drm_device *dev)
> > >  		GT_CONTEXT_SWITCH_INTERRUPT << 
> > > GEN8_VECS_IRQ_SHIFT;
> > >  
> > >  	ring->init_hw = gen8_init_common_ring;
> > > -	if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) 
> > > {
> > > +	if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) 
> > > {
> > >  		ring->get_seqno = bxt_a_get_seqno;
> > >  		ring->set_seqno = bxt_a_set_seqno;
> > >  	} else {
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c 
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index 60d120c472ab..e25791e8748f 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4348,7 +4348,7 @@ static void gen6_set_rps(struct drm_device 
> > > *dev, u8 val)
> > >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > >  
> > >  	/* WaGsvDisableTurbo: Workaround to disable turbo on BXT 
> > > A* */
> > > -	if (IS_BROXTON(dev) && (INTEL_REVID(dev) < 
> > > BXT_REVID_B0))
> > > +	if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= 
> > > BXT_REVID_A1))
> > >  		return;
> > >  
> > >  	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> > > @@ -4672,7 +4672,7 @@ static void gen9_enable_rps(struct 
> > > drm_device *dev)
> > >  	gen6_init_rps_frequencies(dev);
> > >  
> > >  	/* WaGsvDisableTurbo: Workaround to disable turbo on BXT 
> > > A* */
> > > -	if (IS_BROXTON(dev) && (INTEL_REVID(dev) < 
> > > BXT_REVID_B0)) {
> > > +	if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= 
> > > BXT_REVID_A1)) {
> > >  		intel_uncore_forcewake_put(dev_priv, 
> > > FORCEWAKE_ALL);
> > >  		return;
> > >  	}
> > > @@ -4758,7 +4758,7 @@ static void gen9_enable_rc6(struct 
> > > drm_device *dev)
> > >  	 * 3b: Enable Coarse Power Gating only when RC6 is 
> > > enabled.
> > >  	 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media 
> > > PG need to be disabled with RC6.
> > >  	 */
> > > -	if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < 
> > > BXT_REVID_B0)) ||
> > > +	if ((IS_BROXTON(dev) && (INTEL_REVID(dev) <= 
> > > BXT_REVID_A1)) ||
> > >  	    ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && 
> > > (INTEL_REVID(dev) <= SKL_REVID_E0)))
> > >  		I915_WRITE(GEN9_PG_ENABLE, 0);
> > >  	else
> > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> > > b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > index c82c74caa73c..3753e7518d49 100644
> > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > @@ -916,14 +916,14 @@ static int gen9_init_workarounds(struct 
> > > intel_engine_cs *ring)
> > >  
> > >  	if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == 
> > > SKL_REVID_A0 ||
> > >  	    INTEL_REVID(dev) == SKL_REVID_B0)) ||
> > > -	    (IS_BROXTON(dev) && INTEL_REVID(dev) < 
> > > BXT_REVID_B0)) {
> > > +	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= 
> > > BXT_REVID_A1)) {
> > >  		/* 
> > > WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
> > >  		WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> > >  				  GEN9_DG_MIRROR_FIX_ENABLE);
> > >  	}
> > >  
> > >  	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= 
> > > SKL_REVID_B0) ||
> > > -	    (IS_BROXTON(dev) && INTEL_REVID(dev) < 
> > > BXT_REVID_B0)) {
> > > +	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= 
> > > BXT_REVID_A1)) {
> > >  		/* 
> > > WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> > >  		WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> > >  				 
> > >  GEN9_RHWO_OPTIMIZATION_DISABLE);
> > > @@ -952,7 +952,7 @@ static int gen9_init_workarounds(struct 
> > > intel_engine_cs *ring)
> > >  
> > >  	/* WaDisableMaskBasedCammingInRCC:skl,bxt */
> > >  	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == 
> > > SKL_REVID_C0) ||
> > > -	    (IS_BROXTON(dev) && INTEL_REVID(dev) < 
> > > BXT_REVID_B0))
> > > +	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= 
> > > BXT_REVID_A1))
> > >  		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
> > >  				  PIXEL_MASK_CAMMING_DISABLE);
> > >  
> > > -- 
> > > 2.1.4
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Ville Syrjälä
> > Intel OTC
> 
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