From: Ian Campbell <ian.campbell@citrix.com>
To: Julien Grall <julien.grall@citrix.com>, xen-devel@lists.xenproject.org
Cc: stefano.stabellini@eu.citrix.com
Subject: Re: [PATCH v4 1/5] xen/arm: vgic-v2: Handle correctly byte write in ITARGETSR
Date: Fri, 23 Oct 2015 11:12:44 +0100 [thread overview]
Message-ID: <1445595164.2374.104.camel@citrix.com> (raw)
In-Reply-To: <562A04C0.7050109@citrix.com>
On Fri, 2015-10-23 at 10:58 +0100, Julien Grall wrote:
> On 23/10/15 10:33, Ian Campbell wrote:
> > On Thu, 2015-10-22 at 17:36 +0100, Julien Grall wrote:
> > > On 22/10/15 16:53, Ian Campbell wrote:
> > > > On Mon, 2015-10-12 at 15:22 +0100, Julien Grall wrote:
>
> [...]
>
> > > > >
> > > > > Furthermore, the body of the loop is retrieving the old target
> > > > > list
> > > > > using the index of the byte.
> > > > >
> > > > > To avoid modifying too much the loop, shift the byte stored to
> > > > > the
> > > > > correct
> > > > > offset.
> > > >
> > > > That might have meant a smaller patch, but it's a lot harder to
> > > > understand
> > > > either the result or the diff.
> > >
> > > The size of the patch would have been the same. Although, it requires
> > > to
> > > modify the call to vgic_byte_read in the loop to access the correct
> > > interrupt.
> > >
> > > I didn't try to spend to much time to modify the loop because the
> > > follow-up patch (#2) will rewrite the loop.
> >
> > Since this patch is marked for backport then if we decided to take #2
> > then
> > that's probably ok, otherwise the state of the tree after just this
> > patch
> > is more relevant.
> > That's in itself probably a stronger argument for taking #2 than the
> > actual
> > functionality of #2 is.
>
> This code is already complex and I don't think the loop modification would have
> make the code easier to read.
>
> Although, my plan was to ask to backport the whole series once we exercise
> the code a bit in unstable. This is in order to fix 32-bit access on 64-bit
> register.
OK, if the whole series is going to be backported at once then the
maintainability of the intermediate states is not so critical.
Ian.
next prev parent reply other threads:[~2015-10-23 10:12 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-12 14:22 [PATCH v4 0/5] xen/arm: vgic: Support 32-bit access for 64-bit register Julien Grall
2015-10-12 14:22 ` [PATCH v4 1/5] xen/arm: vgic-v2: Handle correctly byte write in ITARGETSR Julien Grall
2015-10-22 15:53 ` Ian Campbell
2015-10-22 16:36 ` Julien Grall
2015-10-23 9:33 ` Ian Campbell
2015-10-23 9:58 ` Julien Grall
2015-10-23 10:12 ` Ian Campbell [this message]
2015-10-12 14:22 ` [PATCH v4 2/5] xen/arm: vgic-v2: Don't ignore a write in ITARGETSR if one field is 0 Julien Grall
2015-10-22 16:07 ` Ian Campbell
2015-10-22 16:51 ` Julien Grall
2015-10-23 9:30 ` Ian Campbell
2015-10-23 9:37 ` Julien Grall
2015-10-23 9:53 ` Ian Campbell
2015-10-12 14:22 ` [PATCH v4 3/5] xen/arm: vgic: Optimize the way to store the target vCPU in the rank Julien Grall
2015-10-22 16:17 ` Ian Campbell
2015-10-22 17:15 ` Julien Grall
2015-10-23 9:34 ` Ian Campbell
2015-10-23 10:01 ` Julien Grall
2015-10-23 10:14 ` Ian Campbell
2015-10-23 10:15 ` Julien Grall
2015-10-12 14:22 ` [PATCH v4 4/5] xen/arm: vgic: Introduce helpers to extract/update/clear/set vGIC register Julien Grall
2015-10-12 14:22 ` [PATCH v4 5/5] xen/arm: vgic-v3: Support 32-bit access for 64-bit registers Julien Grall
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