From: John Snow <jsnow@redhat.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org,
Peter Crosthwaite <crosthwaitepeter@gmail.com>,
jsnow@redhat.com, Peter Crosthwaite <crosthwaite.peter@gmail.com>
Subject: [Qemu-devel] [PULL 2/5] ahci: Add some MMIO debug printfs
Date: Fri, 6 Nov 2015 15:02:28 -0500 [thread overview]
Message-ID: <1446840151-9145-3-git-send-email-jsnow@redhat.com> (raw)
In-Reply-To: <1446840151-9145-1-git-send-email-jsnow@redhat.com>
From: Peter Crosthwaite <crosthwaitepeter@gmail.com>
These are useful for bringup of AHCI.
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Reviewed-by: John Snow <jsnow@redhat.com>
Message-id: 517ba413dce7deb4ab17c0cc1e8bbdaaace2a0db.1445917756.git.crosthwaite.peter@gmail.com
Signed-off-by: John Snow <jsnow@redhat.com>
---
hw/ide/ahci.c | 21 +++++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index f547ebb..7219189 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -378,17 +378,23 @@ static uint64_t ahci_mem_read(void *opaque, hwaddr addr, unsigned size)
int ofst = addr - aligned;
uint64_t lo = ahci_mem_read_32(opaque, aligned);
uint64_t hi;
+ uint64_t val;
/* if < 8 byte read does not cross 4 byte boundary */
if (ofst + size <= 4) {
- return lo >> (ofst * 8);
+ val = lo >> (ofst * 8);
+ } else {
+ g_assert_cmpint(size, >, 1);
+
+ /* If the 64bit read is unaligned, we will produce undefined
+ * results. AHCI does not support unaligned 64bit reads. */
+ hi = ahci_mem_read_32(opaque, aligned + 4);
+ val = (hi << 32 | lo) >> (ofst * 8);
}
- g_assert_cmpint(size, >, 1);
- /* If the 64bit read is unaligned, we will produce undefined
- * results. AHCI does not support unaligned 64bit reads. */
- hi = ahci_mem_read_32(opaque, aligned + 4);
- return (hi << 32 | lo) >> (ofst * 8);
+ DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",
+ addr, val, size);
+ return val;
}
@@ -397,6 +403,9 @@ static void ahci_mem_write(void *opaque, hwaddr addr,
{
AHCIState *s = opaque;
+ DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",
+ addr, val, size);
+
/* Only aligned reads are allowed on AHCI */
if (addr & 3) {
fprintf(stderr, "ahci: Mis-aligned write to addr 0x"
--
2.4.3
next prev parent reply other threads:[~2015-11-06 20:02 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-06 20:02 [Qemu-devel] [PULL 0/5] Ide patches John Snow
2015-11-06 20:02 ` [Qemu-devel] [PULL 1/5] ide: remove hardcoded 2GiB transactional limit John Snow
2015-11-06 20:02 ` John Snow [this message]
2015-11-06 20:02 ` [Qemu-devel] [PULL 3/5] ahci: split realize and init John Snow
2015-11-06 20:02 ` [Qemu-devel] [PULL 4/5] ahci: Add allwinner AHCI John Snow
2015-11-06 20:02 ` [Qemu-devel] [PULL 5/5] arm: allwinner-a10: Add SATA John Snow
2015-11-07 21:41 ` [Qemu-devel] [PULL 0/5] Ide patches Peter Maydell
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