From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 32/77] ppc/xics: Replace "icp" with "xics" in most places
Date: Wed, 11 Nov 2015 11:27:45 +1100 [thread overview]
Message-ID: <1447201710-10229-33-git-send-email-benh@kernel.crashing.org> (raw)
In-Reply-To: <1447201710-10229-1-git-send-email-benh@kernel.crashing.org>
The "ICP" is a different object than the "XICS". For historical reasons,
we have a number of places where we name a variable "icp" while it contains
a XICSState pointer. There *is* an ICPState structure too so this makes
the code really confusing.
This is a mechanical replacement of all those instances to use the name
"xics" instead. There should be no functional change.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
hw/intc/xics.c | 132 ++++++++++++++++++++++----------------------
hw/intc/xics_kvm.c | 54 +++++++++---------
hw/intc/xics_spapr.c | 56 +++++++++----------
hw/ppc/spapr.c | 22 ++++----
hw/ppc/spapr_events.c | 8 +--
hw/ppc/spapr_pci.c | 8 +--
hw/ppc/spapr_vio.c | 2 +-
include/hw/pci-host/spapr.h | 2 +-
include/hw/ppc/spapr.h | 2 +-
include/hw/ppc/spapr_vio.h | 2 +-
include/hw/ppc/xics.h | 2 +-
11 files changed, 145 insertions(+), 145 deletions(-)
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index 197df33..d21471f 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -44,17 +44,17 @@ int get_cpu_index_by_dt_id(int cpu_dt_id)
return -1;
}
-void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu)
+void xics_cpu_setup(XICSState *xics, PowerPCCPU *cpu)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- ICPState *ss = &icp->ss[cs->cpu_index];
- XICSStateClass *info = XICS_COMMON_GET_CLASS(icp);
+ ICPState *ss = &xics->ss[cs->cpu_index];
+ XICSStateClass *info = XICS_COMMON_GET_CLASS(xics);
- assert(cs->cpu_index < icp->nr_servers);
+ assert(cs->cpu_index < xics->nr_servers);
if (info->cpu_setup) {
- info->cpu_setup(icp, cpu);
+ info->cpu_setup(xics, cpu);
}
switch (PPC_INPUT(env)) {
@@ -78,21 +78,21 @@ void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu)
*/
static void xics_common_reset(DeviceState *d)
{
- XICSState *icp = XICS_COMMON(d);
+ XICSState *xics = XICS_COMMON(d);
int i;
- for (i = 0; i < icp->nr_servers; i++) {
- device_reset(DEVICE(&icp->ss[i]));
+ for (i = 0; i < xics->nr_servers; i++) {
+ device_reset(DEVICE(&xics->ss[i]));
}
- device_reset(DEVICE(icp->ics));
+ device_reset(DEVICE(xics->ics));
}
static void xics_prop_get_nr_irqs(Object *obj, Visitor *v,
void *opaque, const char *name, Error **errp)
{
- XICSState *icp = XICS_COMMON(obj);
- int64_t value = icp->nr_irqs;
+ XICSState *xics = XICS_COMMON(obj);
+ int64_t value = xics->nr_irqs;
visit_type_int(v, &value, name, errp);
}
@@ -100,8 +100,8 @@ static void xics_prop_get_nr_irqs(Object *obj, Visitor *v,
static void xics_prop_set_nr_irqs(Object *obj, Visitor *v,
void *opaque, const char *name, Error **errp)
{
- XICSState *icp = XICS_COMMON(obj);
- XICSStateClass *info = XICS_COMMON_GET_CLASS(icp);
+ XICSState *xics = XICS_COMMON(obj);
+ XICSStateClass *info = XICS_COMMON_GET_CLASS(xics);
Error *error = NULL;
int64_t value;
@@ -110,23 +110,23 @@ static void xics_prop_set_nr_irqs(Object *obj, Visitor *v,
error_propagate(errp, error);
return;
}
- if (icp->nr_irqs) {
+ if (xics->nr_irqs) {
error_setg(errp, "Number of interrupts is already set to %u",
- icp->nr_irqs);
+ xics->nr_irqs);
return;
}
assert(info->set_nr_irqs);
- assert(icp->ics);
- info->set_nr_irqs(icp, value, errp);
+ assert(xics->ics);
+ info->set_nr_irqs(xics, value, errp);
}
static void xics_prop_get_nr_servers(Object *obj, Visitor *v,
void *opaque, const char *name,
Error **errp)
{
- XICSState *icp = XICS_COMMON(obj);
- int64_t value = icp->nr_servers;
+ XICSState *xics = XICS_COMMON(obj);
+ int64_t value = xics->nr_servers;
visit_type_int(v, &value, name, errp);
}
@@ -135,8 +135,8 @@ static void xics_prop_set_nr_servers(Object *obj, Visitor *v,
void *opaque, const char *name,
Error **errp)
{
- XICSState *icp = XICS_COMMON(obj);
- XICSStateClass *info = XICS_COMMON_GET_CLASS(icp);
+ XICSState *xics = XICS_COMMON(obj);
+ XICSStateClass *info = XICS_COMMON_GET_CLASS(xics);
Error *error = NULL;
int64_t value;
@@ -145,14 +145,14 @@ static void xics_prop_set_nr_servers(Object *obj, Visitor *v,
error_propagate(errp, error);
return;
}
- if (icp->nr_servers) {
+ if (xics->nr_servers) {
error_setg(errp, "Number of servers is already set to %u",
- icp->nr_servers);
+ xics->nr_servers);
return;
}
assert(info->set_nr_servers);
- info->set_nr_servers(icp, value, errp);
+ info->set_nr_servers(xics, value, errp);
}
static void xics_common_initfn(Object *obj)
@@ -195,9 +195,9 @@ static void ics_reject(ICSState *ics, int nr);
static void ics_resend(ICSState *ics);
static void ics_eoi(ICSState *ics, int nr);
-static void icp_check_ipi(XICSState *icp, int server)
+static void icp_check_ipi(XICSState *xics, int server)
{
- ICPState *ss = icp->ss + server;
+ ICPState *ss = xics->ss + server;
if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
return;
@@ -206,7 +206,7 @@ static void icp_check_ipi(XICSState *icp, int server)
trace_xics_icp_check_ipi(server, ss->mfrr);
if (XISR(ss)) {
- ics_reject(icp->ics, XISR(ss));
+ ics_reject(xics->ics, XISR(ss));
}
ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI;
@@ -214,19 +214,19 @@ static void icp_check_ipi(XICSState *icp, int server)
qemu_irq_raise(ss->output);
}
-static void icp_resend(XICSState *icp, int server)
+static void icp_resend(XICSState *xics, int server)
{
- ICPState *ss = icp->ss + server;
+ ICPState *ss = xics->ss + server;
if (ss->mfrr < CPPR(ss)) {
- icp_check_ipi(icp, server);
+ icp_check_ipi(xics, server);
}
- ics_resend(icp->ics);
+ ics_resend(xics->ics);
}
-void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
+void icp_set_cppr(XICSState *xics, int server, uint8_t cppr)
{
- ICPState *ss = icp->ss + server;
+ ICPState *ss = xics->ss + server;
uint8_t old_cppr;
uint32_t old_xisr;
@@ -239,22 +239,22 @@ void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
ss->xirr &= ~XISR_MASK; /* Clear XISR */
ss->pending_priority = 0xff;
qemu_irq_lower(ss->output);
- ics_reject(icp->ics, old_xisr);
+ ics_reject(xics->ics, old_xisr);
}
} else {
if (!XISR(ss)) {
- icp_resend(icp, server);
+ icp_resend(xics, server);
}
}
}
-void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr)
+void icp_set_mfrr(XICSState *xics, int server, uint8_t mfrr)
{
- ICPState *ss = icp->ss + server;
+ ICPState *ss = xics->ss + server;
ss->mfrr = mfrr;
if (mfrr < CPPR(ss)) {
- icp_check_ipi(icp, server);
+ icp_check_ipi(xics, server);
}
}
@@ -279,31 +279,31 @@ uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr)
return ss->xirr;
}
-void icp_eoi(XICSState *icp, int server, uint32_t xirr)
+void icp_eoi(XICSState *xics, int server, uint32_t xirr)
{
- ICPState *ss = icp->ss + server;
+ ICPState *ss = xics->ss + server;
/* Send EOI -> ICS */
ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
trace_xics_icp_eoi(server, xirr, ss->xirr);
- ics_eoi(icp->ics, xirr & XISR_MASK);
+ ics_eoi(xics->ics, xirr & XISR_MASK);
if (!XISR(ss)) {
- icp_resend(icp, server);
+ icp_resend(xics, server);
}
}
-static void icp_irq(XICSState *icp, int server, int nr, uint8_t priority)
+static void icp_irq(XICSState *xics, int server, int nr, uint8_t priority)
{
- ICPState *ss = icp->ss + server;
+ ICPState *ss = xics->ss + server;
trace_xics_icp_irq(server, nr, priority);
if ((priority >= CPPR(ss))
|| (XISR(ss) && (ss->pending_priority <= priority))) {
- ics_reject(icp->ics, nr);
+ ics_reject(xics->ics, nr);
} else {
if (XISR(ss)) {
- ics_reject(icp->ics, XISR(ss));
+ ics_reject(xics->ics, XISR(ss));
}
ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);
ss->pending_priority = priority;
@@ -388,7 +388,7 @@ static void resend_msi(ICSState *ics, int srcno)
if (irq->status & XICS_STATUS_REJECTED) {
irq->status &= ~XICS_STATUS_REJECTED;
if (irq->priority != 0xff) {
- icp_irq(ics->icp, irq->server, srcno + ics->offset,
+ icp_irq(ics->xics, irq->server, srcno + ics->offset,
irq->priority);
}
}
@@ -402,7 +402,7 @@ static void resend_lsi(ICSState *ics, int srcno)
&& (irq->status & XICS_STATUS_ASSERTED)
&& !(irq->status & XICS_STATUS_SENT)) {
irq->status |= XICS_STATUS_SENT;
- icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
+ icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priority);
}
}
@@ -417,7 +417,7 @@ static void set_irq_msi(ICSState *ics, int srcno, int val)
irq->status |= XICS_STATUS_MASKED_PENDING;
trace_xics_masked_pending();
} else {
- icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
+ icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priority);
}
}
}
@@ -456,7 +456,7 @@ static void write_xive_msi(ICSState *ics, int srcno)
}
irq->status &= ~XICS_STATUS_MASKED_PENDING;
- icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
+ icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priority);
}
static void write_xive_lsi(ICSState *ics, int srcno)
@@ -465,7 +465,7 @@ static void write_xive_lsi(ICSState *ics, int srcno)
}
void ics_write_xive(ICSState *ics, int nr, int server,
- uint8_t priority, uint8_t saved_priority)
+ uint8_t priority, uint8_t saved_priority)
{
int srcno = nr - ics->offset;
ICSIRQState *irq = ics->irqs + srcno;
@@ -541,8 +541,8 @@ static int ics_post_load(ICSState *ics, int version_id)
{
int i;
- for (i = 0; i < ics->icp->nr_servers; i++) {
- icp_resend(ics->icp, i);
+ for (i = 0; i < ics->xics->nr_servers; i++) {
+ icp_resend(ics->xics, i);
}
return 0;
@@ -642,14 +642,14 @@ static const TypeInfo ics_info = {
/*
* Exported functions
*/
-int xics_find_source(XICSState *icp, int irq)
+int xics_find_source(XICSState *xics, int irq)
{
int sources = 1;
int src;
/* FIXME: implement multiple sources */
for (src = 0; src < sources; ++src) {
- ICSState *ics = &icp->ics[src];
+ ICSState *ics = &xics->ics[src];
if (ics_valid_irq(ics, irq)) {
return src;
}
@@ -658,12 +658,12 @@ int xics_find_source(XICSState *icp, int irq)
return -1;
}
-qemu_irq xics_get_qirq(XICSState *icp, int irq)
+qemu_irq xics_get_qirq(XICSState *xics, int irq)
{
- int src = xics_find_source(icp, irq);
+ int src = xics_find_source(xics, irq);
if (src >= 0) {
- ICSState *ics = &icp->ics[src];
+ ICSState *ics = &xics->ics[src];
return ics->qirqs[irq - ics->offset];
}
@@ -682,23 +682,23 @@ void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
* XICS
*/
-void xics_set_nr_irqs(XICSState *icp, uint32_t nr_irqs, Error **errp)
+void xics_set_nr_irqs(XICSState *xics, uint32_t nr_irqs, Error **errp)
{
- icp->nr_irqs = icp->ics->nr_irqs = nr_irqs;
+ xics->nr_irqs = xics->ics->nr_irqs = nr_irqs;
}
-void xics_set_nr_servers(XICSState *icp, uint32_t nr_servers, Error **errp)
+void xics_set_nr_servers(XICSState *xics, uint32_t nr_servers, Error **errp)
{
int i;
- icp->nr_servers = nr_servers;
+ xics->nr_servers = nr_servers;
- icp->ss = g_malloc0(icp->nr_servers*sizeof(ICPState));
- for (i = 0; i < icp->nr_servers; i++) {
+ xics->ss = g_malloc0(xics->nr_servers*sizeof(ICPState));
+ for (i = 0; i < xics->nr_servers; i++) {
char buffer[32];
- object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_ICP);
+ object_initialize(&xics->ss[i], sizeof(xics->ss[i]), TYPE_ICP);
snprintf(buffer, sizeof(buffer), "icp[%d]", i);
- object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]),
+ object_property_add_child(OBJECT(xics), buffer, OBJECT(&xics->ss[i]),
errp);
}
}
diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c
index 03ae801..7d86157 100644
--- a/hw/intc/xics_kvm.c
+++ b/hw/intc/xics_kvm.c
@@ -138,7 +138,7 @@ static const TypeInfo icp_kvm_info = {
*/
static void ics_get_kvm_state(ICSState *ics)
{
- KVMXICSState *icpkvm = KVM_XICS(ics->icp);
+ KVMXICSState *xicskvm = KVM_XICS(ics->xics);
uint64_t state;
struct kvm_device_attr attr = {
.flags = 0,
@@ -153,7 +153,7 @@ static void ics_get_kvm_state(ICSState *ics)
attr.attr = i + ics->offset;
- ret = ioctl(icpkvm->kernel_xics_fd, KVM_GET_DEVICE_ATTR, &attr);
+ ret = ioctl(xicskvm->kernel_xics_fd, KVM_GET_DEVICE_ATTR, &attr);
if (ret != 0) {
error_report("Unable to retrieve KVM interrupt controller state"
" for IRQ %d: %s", i + ics->offset, strerror(errno));
@@ -197,7 +197,7 @@ static void ics_get_kvm_state(ICSState *ics)
static int ics_set_kvm_state(ICSState *ics, int version_id)
{
- KVMXICSState *icpkvm = KVM_XICS(ics->icp);
+ KVMXICSState *xicskvm = KVM_XICS(ics->xics);
uint64_t state;
struct kvm_device_attr attr = {
.flags = 0,
@@ -231,7 +231,7 @@ static int ics_set_kvm_state(ICSState *ics, int version_id)
}
}
- ret = ioctl(icpkvm->kernel_xics_fd, KVM_SET_DEVICE_ATTR, &attr);
+ ret = ioctl(xicskvm->kernel_xics_fd, KVM_SET_DEVICE_ATTR, &attr);
if (ret != 0) {
error_report("Unable to restore KVM interrupt controller state"
" for IRQs %d: %s", i + ics->offset, strerror(errno));
@@ -317,17 +317,17 @@ static const TypeInfo ics_kvm_info = {
/*
* XICS-KVM
*/
-static void xics_kvm_cpu_setup(XICSState *icp, PowerPCCPU *cpu)
+static void xics_kvm_cpu_setup(XICSState *xics, PowerPCCPU *cpu)
{
CPUState *cs;
ICPState *ss;
- KVMXICSState *icpkvm = KVM_XICS(icp);
+ KVMXICSState *xicskvm = KVM_XICS(xics);
cs = CPU(cpu);
- ss = &icp->ss[cs->cpu_index];
+ ss = &xics->ss[cs->cpu_index];
- assert(cs->cpu_index < icp->nr_servers);
- if (icpkvm->kernel_xics_fd == -1) {
+ assert(cs->cpu_index < xics->nr_servers);
+ if (xicskvm->kernel_xics_fd == -1) {
abort();
}
@@ -340,13 +340,13 @@ static void xics_kvm_cpu_setup(XICSState *icp, PowerPCCPU *cpu)
return;
}
- if (icpkvm->kernel_xics_fd != -1) {
+ if (xicskvm->kernel_xics_fd != -1) {
int ret;
ss->cs = cs;
ret = kvm_vcpu_enable_cap(cs, KVM_CAP_IRQ_XICS, 0,
- icpkvm->kernel_xics_fd, kvm_arch_vcpu_id(cs));
+ xicskvm->kernel_xics_fd, kvm_arch_vcpu_id(cs));
if (ret < 0) {
error_report("Unable to connect CPU%ld to kernel XICS: %s",
kvm_arch_vcpu_id(cs), strerror(errno));
@@ -356,24 +356,24 @@ static void xics_kvm_cpu_setup(XICSState *icp, PowerPCCPU *cpu)
}
}
-static void xics_kvm_set_nr_irqs(XICSState *icp, uint32_t nr_irqs, Error **errp)
+static void xics_kvm_set_nr_irqs(XICSState *xics, uint32_t nr_irqs, Error **errp)
{
- icp->nr_irqs = icp->ics->nr_irqs = nr_irqs;
+ xics->nr_irqs = xics->ics->nr_irqs = nr_irqs;
}
-static void xics_kvm_set_nr_servers(XICSState *icp, uint32_t nr_servers,
+static void xics_kvm_set_nr_servers(XICSState *xics, uint32_t nr_servers,
Error **errp)
{
int i;
- icp->nr_servers = nr_servers;
+ xics->nr_servers = nr_servers;
- icp->ss = g_malloc0(icp->nr_servers*sizeof(ICPState));
- for (i = 0; i < icp->nr_servers; i++) {
+ xics->ss = g_malloc0(xics->nr_servers*sizeof(ICPState));
+ for (i = 0; i < xics->nr_servers; i++) {
char buffer[32];
- object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_KVM_ICP);
+ object_initialize(&xics->ss[i], sizeof(xics->ss[i]), TYPE_KVM_ICP);
snprintf(buffer, sizeof(buffer), "icp[%d]", i);
- object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]),
+ object_property_add_child(OBJECT(xics), buffer, OBJECT(&xics->ss[i]),
errp);
}
}
@@ -389,8 +389,8 @@ static void rtas_dummy(PowerPCCPU *cpu, sPAPRMachineState *spapr,
static void xics_kvm_realize(DeviceState *dev, Error **errp)
{
- KVMXICSState *icpkvm = KVM_XICS(dev);
- XICSState *icp = XICS_COMMON(dev);
+ KVMXICSState *xicskvm = KVM_XICS(dev);
+ XICSState *xics = XICS_COMMON(dev);
int i, rc;
Error *error = NULL;
struct kvm_create_device xics_create_device = {
@@ -440,17 +440,17 @@ static void xics_kvm_realize(DeviceState *dev, Error **errp)
goto fail;
}
- icpkvm->kernel_xics_fd = xics_create_device.fd;
+ xicskvm->kernel_xics_fd = xics_create_device.fd;
- object_property_set_bool(OBJECT(icp->ics), true, "realized", &error);
+ object_property_set_bool(OBJECT(xics->ics), true, "realized", &error);
if (error) {
error_propagate(errp, error);
goto fail;
}
- assert(icp->nr_servers);
- for (i = 0; i < icp->nr_servers; i++) {
- object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", &error);
+ assert(xics->nr_servers);
+ for (i = 0; i < xics->nr_servers; i++) {
+ object_property_set_bool(OBJECT(&xics->ss[i]), true, "realized", &error);
if (error) {
error_propagate(errp, error);
goto fail;
@@ -476,7 +476,7 @@ static void xics_kvm_initfn(Object *obj)
xics->ics = ICS(object_new(TYPE_KVM_ICS));
object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);
- xics->ics->icp = xics;
+ xics->ics->xics = xics;
}
static void xics_kvm_class_init(ObjectClass *oc, void *data)
diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
index aae1665..fb508cd 100644
--- a/hw/intc/xics_spapr.c
+++ b/hw/intc/xics_spapr.c
@@ -43,7 +43,7 @@ static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
CPUState *cs = CPU(cpu);
target_ulong cppr = args[0];
- icp_set_cppr(spapr->icp, cs->cpu_index, cppr);
+ icp_set_cppr(spapr->xics, cs->cpu_index, cppr);
return H_SUCCESS;
}
@@ -53,11 +53,11 @@ static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong server = get_cpu_index_by_dt_id(args[0]);
target_ulong mfrr = args[1];
- if (server >= spapr->icp->nr_servers) {
+ if (server >= spapr->xics->nr_servers) {
return H_PARAMETER;
}
- icp_set_mfrr(spapr->icp, server, mfrr);
+ icp_set_mfrr(spapr->xics, server, mfrr);
return H_SUCCESS;
}
@@ -65,7 +65,7 @@ static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
CPUState *cs = CPU(cpu);
- uint32_t xirr = icp_accept(spapr->icp->ss + cs->cpu_index);
+ uint32_t xirr = icp_accept(spapr->xics->ss + cs->cpu_index);
args[0] = xirr;
return H_SUCCESS;
@@ -75,7 +75,7 @@ static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
CPUState *cs = CPU(cpu);
- ICPState *ss = &spapr->icp->ss[cs->cpu_index];
+ ICPState *ss = &spapr->xics->ss[cs->cpu_index];
uint32_t xirr = icp_accept(ss);
args[0] = xirr;
@@ -89,7 +89,7 @@ static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
CPUState *cs = CPU(cpu);
target_ulong xirr = args[0];
- icp_eoi(spapr->icp, cs->cpu_index, xirr);
+ icp_eoi(spapr->xics, cs->cpu_index, xirr);
return H_SUCCESS;
}
@@ -98,7 +98,7 @@ static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr,
{
CPUState *cs = CPU(cpu);
uint32_t mfrr;
- uint32_t xirr = icp_ipoll(spapr->icp->ss + cs->cpu_index, &mfrr);
+ uint32_t xirr = icp_ipoll(spapr->xics->ss + cs->cpu_index, &mfrr);
args[0] = xirr;
args[1] = mfrr;
@@ -111,7 +111,7 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
uint32_t nargs, target_ulong args,
uint32_t nret, target_ulong rets)
{
- ICSState *ics = spapr->icp->ics;
+ ICSState *ics = spapr->xics->ics;
uint32_t nr, server, priority;
if ((nargs != 3) || (nret != 1)) {
@@ -123,7 +123,7 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
server = get_cpu_index_by_dt_id(rtas_ld(args, 1));
priority = rtas_ld(args, 2);
- if (!ics_valid_irq(ics, nr) || (server >= ics->icp->nr_servers)
+ if (!ics_valid_irq(ics, nr) || (server >= ics->xics->nr_servers)
|| (priority > 0xff)) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
return;
@@ -139,7 +139,7 @@ static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
uint32_t nargs, target_ulong args,
uint32_t nret, target_ulong rets)
{
- ICSState *ics = spapr->icp->ics;
+ ICSState *ics = spapr->xics->ics;
uint32_t nr;
if ((nargs != 1) || (nret != 3)) {
@@ -164,7 +164,7 @@ static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,
uint32_t nargs, target_ulong args,
uint32_t nret, target_ulong rets)
{
- ICSState *ics = spapr->icp->ics;
+ ICSState *ics = spapr->xics->ics;
uint32_t nr;
if ((nargs != 1) || (nret != 1)) {
@@ -190,7 +190,7 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
uint32_t nargs, target_ulong args,
uint32_t nret, target_ulong rets)
{
- ICSState *ics = spapr->icp->ics;
+ ICSState *ics = spapr->xics->ics;
uint32_t nr;
if ((nargs != 1) || (nret != 1)) {
@@ -214,11 +214,11 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
static void xics_spapr_realize(DeviceState *dev, Error **errp)
{
- XICSState *icp = XICS(dev);
+ XICSState *xics = XICS(dev);
Error *error = NULL;
int i;
- if (!icp->nr_servers) {
+ if (!xics->nr_servers) {
error_setg(errp, "Number of servers needs to be greater 0");
return;
}
@@ -236,14 +236,14 @@ static void xics_spapr_realize(DeviceState *dev, Error **errp)
spapr_register_hypercall(H_EOI, h_eoi);
spapr_register_hypercall(H_IPOLL, h_ipoll);
- object_property_set_bool(OBJECT(icp->ics), true, "realized", &error);
+ object_property_set_bool(OBJECT(xics->ics), true, "realized", &error);
if (error) {
error_propagate(errp, error);
return;
}
- for (i = 0; i < icp->nr_servers; i++) {
- object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", &error);
+ for (i = 0; i < xics->nr_servers; i++) {
+ object_property_set_bool(OBJECT(&xics->ss[i]), true, "realized", &error);
if (error) {
error_propagate(errp, error);
return;
@@ -257,7 +257,7 @@ static void xics_spapr_initfn(Object *obj)
xics->ics = ICS(object_new(TYPE_ICS));
object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);
- xics->ics->icp = xics;
+ xics->ics->xics = xics;
}
static void xics_spapr_class_init(ObjectClass *oc, void *data)
@@ -303,13 +303,13 @@ static int ics_find_free_block(ICSState *ics, int num, int alignnum)
return -1;
}
-int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi)
+int xics_spapr_alloc(XICSState *xics, int src, int irq_hint, bool lsi)
{
- ICSState *ics = &icp->ics[src];
+ ICSState *ics = &xics->ics[src];
int irq;
if (irq_hint) {
- assert(src == xics_find_source(icp, irq_hint));
+ assert(src == xics_find_source(xics, irq_hint));
if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) {
trace_xics_alloc_failed_hint(src, irq_hint);
return -1;
@@ -334,10 +334,10 @@ int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi)
* Allocate block of consecutive IRQs, and return the number of the first IRQ in the block.
* If align==true, aligns the first IRQ number to num.
*/
-int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi, bool align)
+int xics_spapr_alloc_block(XICSState *xics, int src, int num, bool lsi, bool align)
{
int i, first = -1;
- ICSState *ics = &icp->ics[src];
+ ICSState *ics = &xics->ics[src];
assert(src == 0);
/*
@@ -373,23 +373,23 @@ static void ics_free(ICSState *ics, int srcno, int num)
for (i = srcno; i < srcno + num; ++i) {
if (ICS_IRQ_FREE(ics, i)) {
- trace_xics_ics_free_warn(ics - ics->icp->ics, i + ics->offset);
+ trace_xics_ics_free_warn(ics - ics->xics->ics, i + ics->offset);
}
memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
}
}
-void xics_spapr_free(XICSState *icp, int irq, int num)
+void xics_spapr_free(XICSState *xics, int irq, int num)
{
- int src = xics_find_source(icp, irq);
+ int src = xics_find_source(xics, irq);
if (src >= 0) {
- ICSState *ics = &icp->ics[src];
+ ICSState *ics = &xics->ics[src];
/* FIXME: implement multiple sources */
assert(src == 0);
- trace_xics_ics_free(ics - icp->ics, irq, num);
+ trace_xics_ics_free(ics - xics->ics, irq, num);
ics_free(ics, irq - ics->offset, num);
}
}
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index bf94426..d8a84ca 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -113,25 +113,25 @@ static XICSState *try_create_xics(const char *type, int nr_servers,
static XICSState *xics_system_init(MachineState *machine,
int nr_servers, int nr_irqs)
{
- XICSState *icp = NULL;
+ XICSState *xics = NULL;
if (kvm_enabled()) {
Error *err = NULL;
if (machine_kernel_irqchip_allowed(machine)) {
- icp = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs, &err);
+ xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs, &err);
}
- if (machine_kernel_irqchip_required(machine) && !icp) {
+ if (machine_kernel_irqchip_required(machine) && !xics) {
error_report("kernel_irqchip requested but unavailable: %s",
error_get_pretty(err));
}
}
- if (!icp) {
- icp = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, &error_abort);
+ if (!xics) {
+ xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, &error_abort);
}
- return icp;
+ return xics;
}
static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
@@ -1615,7 +1615,7 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu)
}
}
- xics_cpu_setup(spapr->icp, cpu);
+ xics_cpu_setup(spapr->xics, cpu);
qemu_register_reset(spapr_cpu_reset, cpu);
}
@@ -1765,10 +1765,10 @@ static void ppc_spapr_init(MachineState *machine)
spapr_alloc_htab(spapr);
/* Set up Interrupt Controller before we create the VCPUs */
- spapr->icp = xics_system_init(machine,
- DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(),
- smp_threads),
- XICS_IRQS_SPAPR);
+ spapr->xics = xics_system_init(machine,
+ DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(),
+ smp_threads),
+ XICS_IRQS_SPAPR);
if (smc->dr_lmb_enabled) {
spapr_validate_node_memory(machine);
diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c
index 3b3663e..c06deea 100644
--- a/hw/ppc/spapr_events.c
+++ b/hw/ppc/spapr_events.c
@@ -383,7 +383,7 @@ static void spapr_powerdown_req(Notifier *n, void *opaque)
rtas_event_log_queue(RTAS_LOG_TYPE_EPOW, new_epow, true);
- qemu_irq_pulse(xics_get_qirq(spapr->icp, spapr->check_exception_irq));
+ qemu_irq_pulse(xics_get_qirq(spapr->xics, spapr->check_exception_irq));
}
static void spapr_hotplug_req_event(uint8_t hp_id, uint8_t hp_action,
@@ -452,7 +452,7 @@ static void spapr_hotplug_req_event(uint8_t hp_id, uint8_t hp_action,
rtas_event_log_queue(RTAS_LOG_TYPE_HOTPLUG, new_hp, true);
- qemu_irq_pulse(xics_get_qirq(spapr->icp, spapr->check_exception_irq));
+ qemu_irq_pulse(xics_get_qirq(spapr->xics, spapr->check_exception_irq));
}
void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc)
@@ -535,7 +535,7 @@ static void check_exception(PowerPCCPU *cpu, sPAPRMachineState *spapr,
* interrupts.
*/
if (rtas_event_log_contains(mask, true)) {
- qemu_irq_pulse(xics_get_qirq(spapr->icp, spapr->check_exception_irq));
+ qemu_irq_pulse(xics_get_qirq(spapr->xics, spapr->check_exception_irq));
}
return;
@@ -587,7 +587,7 @@ out_no_events:
void spapr_events_init(sPAPRMachineState *spapr)
{
QTAILQ_INIT(&spapr->pending_events);
- spapr->check_exception_irq = xics_spapr_alloc(spapr->icp, 0, 0, false);
+ spapr->check_exception_irq = xics_spapr_alloc(spapr->xics, 0, 0, false);
spapr->epow_notifier.notify = spapr_powerdown_req;
qemu_register_powerdown_notifier(&spapr->epow_notifier);
spapr_rtas_register(RTAS_CHECK_EXCEPTION, "check-exception",
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 8b613a8..cf3192e 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -313,7 +313,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
return;
}
- xics_spapr_free(spapr->icp, msi->first_irq, msi->num);
+ xics_spapr_free(spapr->xics, msi->first_irq, msi->num);
if (msi_present(pdev)) {
spapr_msi_setmsg(pdev, 0, false, 0, num);
}
@@ -351,7 +351,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
}
/* Allocate MSIs */
- irq = xics_spapr_alloc_block(spapr->icp, 0, req_num, false,
+ irq = xics_spapr_alloc_block(spapr->xics, 0, req_num, false,
ret_intr_type == RTAS_TYPE_MSI);
if (!irq) {
error_report("Cannot allocate MSIs for device %x", config_addr);
@@ -729,7 +729,7 @@ static void spapr_msi_write(void *opaque, hwaddr addr,
trace_spapr_pci_msi_write(addr, data, irq);
- qemu_irq_pulse(xics_get_qirq(spapr->icp, irq));
+ qemu_irq_pulse(xics_get_qirq(spapr->xics, irq));
}
static const MemoryRegionOps spapr_msi_ops = {
@@ -1360,7 +1360,7 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
for (i = 0; i < PCI_NUM_PINS; i++) {
uint32_t irq;
- irq = xics_spapr_alloc_block(spapr->icp, 0, 1, true, false);
+ irq = xics_spapr_alloc_block(spapr->xics, 0, 1, true, false);
if (!irq) {
error_setg(errp, "spapr_allocate_lsi failed");
return;
diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
index 7b718cc..fc731eb 100644
--- a/hw/ppc/spapr_vio.c
+++ b/hw/ppc/spapr_vio.c
@@ -462,7 +462,7 @@ static void spapr_vio_busdev_realize(DeviceState *qdev, Error **errp)
dev->qdev.id = id;
}
- dev->irq = xics_spapr_alloc(spapr->icp, 0, dev->irq, false);
+ dev->irq = xics_spapr_alloc(spapr->xics, 0, dev->irq, false);
if (!dev->irq) {
error_setg(errp, "can't allocate IRQ");
return;
diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h
index 7de5e02..117c1f8 100644
--- a/include/hw/pci-host/spapr.h
+++ b/include/hw/pci-host/spapr.h
@@ -120,7 +120,7 @@ static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
{
sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
- return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq);
+ return xics_get_qirq(spapr->xics, phb->lsi_table[pin].irq);
}
PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index);
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 5baa906..c6a0136 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -48,7 +48,7 @@ struct sPAPRMachineState {
struct VIOsPAPRBus *vio_bus;
QLIST_HEAD(, sPAPRPHBState) phbs;
struct sPAPRNVRAM *nvram;
- XICSState *icp;
+ XICSState *xics;
DeviceState *rtc;
void *htab;
diff --git a/include/hw/ppc/spapr_vio.h b/include/hw/ppc/spapr_vio.h
index 2299a54..e10fd52 100644
--- a/include/hw/ppc/spapr_vio.h
+++ b/include/hw/ppc/spapr_vio.h
@@ -90,7 +90,7 @@ static inline qemu_irq spapr_vio_qirq(VIOsPAPRDevice *dev)
{
sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
- return xics_get_qirq(spapr->icp, dev->irq);
+ return xics_get_qirq(spapr->xics, dev->irq);
}
static inline bool spapr_vio_dma_valid(VIOsPAPRDevice *dev, uint64_t taddr,
diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index 8e7998f..e670e89 100644
--- a/include/hw/ppc/xics.h
+++ b/include/hw/ppc/xics.h
@@ -138,7 +138,7 @@ struct ICSState {
uint32_t offset;
qemu_irq *qirqs;
ICSIRQState *irqs;
- XICSState *icp;
+ XICSState *xics;
};
static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
--
2.5.0
next prev parent reply other threads:[~2015-11-11 0:30 UTC|newest]
Thread overview: 198+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-11 0:27 [Qemu-devel] [PATCH 00/77] ppc: Add "native" POWER8 platform Benjamin Herrenschmidt
2015-11-11 0:27 ` [Qemu-devel] [PATCH 01/77] ppc: Remove MMU_MODEn_SUFFIX definitions Benjamin Herrenschmidt
2015-11-11 0:27 ` [Qemu-devel] [PATCH 02/77] ppc: Use split I/D mmu modes to avoid flushes on interrupts Benjamin Herrenschmidt
2015-11-16 4:49 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-16 10:10 ` Benjamin Herrenschmidt
2015-11-16 12:42 ` David Gibson
2015-11-27 10:29 ` Alexander Graf
2015-11-27 12:15 ` Paolo Bonzini
2015-11-11 0:27 ` [Qemu-devel] [PATCH 03/77] ppc: Do some batching of TCG tlb flushes Benjamin Herrenschmidt
2015-11-16 5:00 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-16 10:16 ` Benjamin Herrenschmidt
2015-11-19 6:09 ` David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 04/77] target-ppc: Use sensible POWER8/POWER8E versions Benjamin Herrenschmidt
2015-11-11 0:59 ` [Qemu-devel] [Qemu-ppc] " Stewart Smith
2015-11-16 5:01 ` David Gibson
2015-11-16 10:17 ` Benjamin Herrenschmidt
2015-11-17 0:11 ` Alexey Kardashevskiy
2015-11-17 0:40 ` Benjamin Herrenschmidt
2015-11-11 0:27 ` [Qemu-devel] [PATCH 05/77] ppc: Update SPR definitions Benjamin Herrenschmidt
2015-11-16 5:06 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 06/77] ppc: Add macros to register hypervisor mode SPRs Benjamin Herrenschmidt
2015-11-16 5:09 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 07/77] ppc: Add a bunch of hypervisor SPRs to Book3s Benjamin Herrenschmidt
2015-11-19 6:11 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-19 10:21 ` Benjamin Herrenschmidt
2015-11-11 0:27 ` [Qemu-devel] [PATCH 08/77] ppc: Add number of threads per core to the processor definition Benjamin Herrenschmidt
2015-11-16 5:16 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-20 0:29 ` Benjamin Herrenschmidt
2015-11-11 0:27 ` [Qemu-devel] [PATCH 09/77] ppc: Fix do_rfi() for rfi emulation Benjamin Herrenschmidt
2015-11-19 6:19 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-19 10:23 ` Benjamin Herrenschmidt
2015-11-20 0:26 ` Benjamin Herrenschmidt
2015-11-11 0:27 ` [Qemu-devel] [PATCH 10/77] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV Benjamin Herrenschmidt
2015-11-19 6:20 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 11/77] ppc: Create cpu_ppc_set_papr() helper Benjamin Herrenschmidt
2015-11-16 5:30 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 12/77] ppc: Better figure out if processor has HV mode Benjamin Herrenschmidt
2015-11-19 6:22 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 13/77] ppc: tlbie, tlbia and tlbisync are HV only Benjamin Herrenschmidt
2015-11-16 5:34 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-16 10:21 ` Benjamin Herrenschmidt
2015-11-18 0:06 ` Benjamin Herrenschmidt
2015-11-11 0:27 ` [Qemu-devel] [PATCH 14/77] ppc: Change 'invalid' bit mask of tlbiel and tlbie Benjamin Herrenschmidt
2015-11-20 7:02 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 15/77] ppc: Fix sign extension issue in mtmsr(d) emulation Benjamin Herrenschmidt
2015-11-19 6:26 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-19 10:26 ` Benjamin Herrenschmidt
2015-11-11 0:27 ` [Qemu-devel] [PATCH 16/77] ppc: Get out of emulation on SMT "OR" ops Benjamin Herrenschmidt
2015-11-16 5:40 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 17/77] ppc: Add PPC_64H instruction flag to POWER7 and POWER8 Benjamin Herrenschmidt
2015-11-16 5:41 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 18/77] ppc: Rework POWER7 & POWER8 exception model Benjamin Herrenschmidt
2015-11-19 6:44 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-19 10:31 ` Benjamin Herrenschmidt
2015-11-11 0:27 ` [Qemu-devel] [PATCH 19/77] ppc: Fix POWER7 and POWER8 exception definitions Benjamin Herrenschmidt
2015-11-19 6:46 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 20/77] ppc: Fix generation if ISI/DSI vs. HV mode Benjamin Herrenschmidt
2015-11-19 6:50 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 21/77] ppc: Rework generation of priv and inval interrupts Benjamin Herrenschmidt
2015-11-20 7:45 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-24 0:44 ` Benjamin Herrenschmidt
2015-11-24 2:22 ` David Gibson
2015-11-24 0:51 ` Benjamin Herrenschmidt
2015-11-24 2:22 ` David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 22/77] ppc: Add real mode CI load/store instructions for P7 and P8 Benjamin Herrenschmidt
2015-11-20 7:48 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-24 0:58 ` Benjamin Herrenschmidt
2015-11-11 0:27 ` [Qemu-devel] [PATCH 23/77] ppc: Turn a bunch of booleans from int to bool Benjamin Herrenschmidt
2015-11-20 7:49 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 24/77] ppc: Move exception generation code out of line Benjamin Herrenschmidt
2015-11-20 7:53 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-24 0:59 ` Benjamin Herrenschmidt
2015-11-11 0:27 ` [Qemu-devel] [PATCH 25/77] ppc: Add P7/P8 Power Management instructions Benjamin Herrenschmidt
2015-11-20 8:06 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 26/77] ppc/pnv: Add skeletton PowerNV platform Benjamin Herrenschmidt
2015-11-19 8:58 ` [Qemu-devel] [Qemu-ppc] " Stewart Smith
2015-11-20 8:21 ` David Gibson
2015-11-24 1:45 ` Benjamin Herrenschmidt
2015-11-24 2:43 ` David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 27/77] ppc/pnv: Add XSCOM infrastructure Benjamin Herrenschmidt
2015-11-24 3:20 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-24 8:49 ` Benjamin Herrenschmidt
2015-11-24 8:55 ` Benjamin Herrenschmidt
2015-11-11 0:27 ` [Qemu-devel] [PATCH 28/77] ppc/xics: Rename existing XICS classe to XICS_SPAPR Benjamin Herrenschmidt
2015-11-24 3:25 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 29/77] ppc/xics: Move SPAPR specific code to a separate file Benjamin Herrenschmidt
2015-11-24 3:32 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 30/77] ppc/xics: Implement H_IPOLL using an accessor Benjamin Herrenschmidt
2015-11-11 0:27 ` [Qemu-devel] [PATCH 31/77] ppc/xics: Remove unused xics_set_irq_type() Benjamin Herrenschmidt
2015-11-24 3:34 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` Benjamin Herrenschmidt [this message]
2015-11-24 3:36 ` [Qemu-devel] [Qemu-ppc] [PATCH 32/77] ppc/xics: Replace "icp" with "xics" in most places David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 33/77] ppc/xics: Make the ICSState a list Benjamin Herrenschmidt
2015-12-01 4:30 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 34/77] ppc/xics: An ICS with offset 0 is assumed to be uninitialized Benjamin Herrenschmidt
2015-12-01 4:40 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 35/77] ppc/xics: Move xics_set_nr_irqs() to xics_spapr.c and xics_kvm.c Benjamin Herrenschmidt
2015-12-01 4:46 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 36/77] ppc/xics: Use a helper to add a new ICS Benjamin Herrenschmidt
2015-12-01 4:47 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 37/77] ppc/xics: Split ICS into base class and "simple" implementation Benjamin Herrenschmidt
2015-12-01 5:13 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 38/77] ppc/xics: Add "native" XICS subclass Benjamin Herrenschmidt
2015-12-01 6:28 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-12-01 6:39 ` David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 39/77] ppc/xics: Add xics to the monitor "info pic" command Benjamin Herrenschmidt
2015-12-01 6:32 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 40/77] ppc/pnv: Wire up XICS native with PowerNV platform Benjamin Herrenschmidt
2015-12-01 6:41 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-11-11 0:27 ` [Qemu-devel] [PATCH 41/77] ppc/pnv: Add LPC controller and hook it up with a UART and RTC Benjamin Herrenschmidt
2015-11-17 0:32 ` Alexey Kardashevskiy
2015-11-17 0:40 ` Benjamin Herrenschmidt
2015-12-01 6:43 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2015-12-02 2:24 ` Alexey Kardashevskiy
2015-12-02 5:29 ` Benjamin Herrenschmidt
2015-12-03 1:04 ` Alexey Kardashevskiy
2015-12-03 1:45 ` David Gibson
2015-12-03 22:58 ` Benjamin Herrenschmidt
2015-12-03 22:54 ` Benjamin Herrenschmidt
2015-11-11 0:27 ` [Qemu-devel] [PATCH 42/77] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt Benjamin Herrenschmidt
2015-11-11 0:27 ` [Qemu-devel] [PATCH 43/77] ppc/pnv: Add OCC model stub with interrupt support Benjamin Herrenschmidt
2015-11-11 0:27 ` [Qemu-devel] [PATCH 44/77] pci-bridge: Set a supported devfn_min for bridge Benjamin Herrenschmidt
2015-11-18 12:31 ` Paolo Bonzini
2015-11-18 12:41 ` [Qemu-devel] [PATCH for-2.5 " Paolo Bonzini
2015-11-18 14:21 ` Michael S. Tsirkin
2015-11-18 14:25 ` Paolo Bonzini
2015-11-18 16:38 ` Michael S. Tsirkin
2015-11-11 0:27 ` [Qemu-devel] [PATCH 45/77] qdev: Add a hook for a bus to device if it can add devices Benjamin Herrenschmidt
2015-11-18 12:34 ` Paolo Bonzini
2015-11-18 20:06 ` Benjamin Herrenschmidt
2015-11-11 0:27 ` [Qemu-devel] [PATCH 46/77] pci: Use the new pci_can_add_device() to enforce devfn_min/max Benjamin Herrenschmidt
2015-11-18 12:35 ` Paolo Bonzini
2015-11-11 0:28 ` [Qemu-devel] [PATCH 47/77] pci: Don't call pci_irq_handler() for a negative intx Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 48/77] ppc/pnv: Add model for Power8 PHB3 PCIe Host bridge Benjamin Herrenschmidt
2017-03-17 8:24 ` [Qemu-devel] [Qemu-ppc] " Cédric Le Goater
2017-03-17 22:15 ` Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 49/77] ppc/pnv: Create a default PCI layout Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 50/77] ppc: Update LPCR definitions Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 51/77] ppc: Use a helper to filter writes to LPCR Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 52/77] ppc: Cosmetic, align some comments Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 53/77] ppc: Add proper real mode translation support Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 54/77] ppc: Fix 64K pages support in full emulation Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 55/77] ppc/pnv+spapr: Add "ibm, pa-features" property to the device-tree Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 56/77] ppc: Fix conditions for delivering external interrupts to a guest Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 57/77] ppc: Enforce setting MSR:EE, IR and DR when MSR:PR is set Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 58/77] ppc: Initial HDEC support Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 59/77] ppc: Add placeholder SPRs for DPDES and DHDES on P8 Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 60/77] ppc: LPCR is a HV resource Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 61/77] ppc: SPURR & PURR are HV writeable and privileged Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 62/77] ppc: Add dummy SPR_IC for POWER8 Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 63/77] ppc: Initialize AMOR in PAPR mode Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 64/77] ppc: Fix writing to AMR/UAMOR Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 65/77] ppc: Add POWER8 IAMR register Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 66/77] ppc: Add a few more P8 PMU SPRs Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 67/77] ppc: Add dummy write to VTB Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 68/77] ppc: Add dummy POWER8 MPPR register Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 69/77] ppc: Add dummy POWER8 PSPB SPR Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 70/77] ppc: Add dummy CIABR SPR Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 71/77] ppc: Add dummy ACOP SPR Benjamin Herrenschmidt
2016-03-02 20:22 ` Thomas Huth
2015-11-11 0:28 ` [Qemu-devel] [PATCH 72/77] ppc: A couple more dummy POWER8 Book4 regs Benjamin Herrenschmidt
2016-03-02 20:30 ` Thomas Huth
2016-03-04 0:59 ` Benjamin Herrenschmidt
2016-03-09 20:04 ` [Qemu-devel] [Qemu-ppc] " Cédric Le Goater
2016-03-09 21:17 ` Thomas Huth
2016-03-10 18:01 ` Thomas Huth
2016-03-10 22:27 ` Cédric Le Goater
2016-03-11 10:04 ` Thomas Huth
2016-03-11 14:22 ` Cédric Le Goater
2016-03-11 14:46 ` Thomas Huth
2016-03-14 14:53 ` Cédric Le Goater
2016-03-14 15:43 ` Thomas Huth
2016-03-14 15:50 ` Cédric Le Goater
2015-11-11 0:28 ` [Qemu-devel] [PATCH 73/77] ppc: Add KVM numbers to some P8 SPRs Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 74/77] ppc: Print HSRR0/HSRR1 in "info registers" Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 75/77] ppc: Add dummy logmpp instruction Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 76/77] ppc: Add slbfee. instruction Benjamin Herrenschmidt
2015-11-11 0:28 ` [Qemu-devel] [PATCH 77/77] ppc: Fix CFAR updates Benjamin Herrenschmidt
2015-11-11 0:42 ` [Qemu-devel] [Qemu-ppc] [PATCH 00/77] ppc: Add "native" POWER8 platform Benjamin Herrenschmidt
2015-11-11 0:50 ` [Qemu-devel] " Eric Blake
2015-11-11 0:56 ` Benjamin Herrenschmidt
2015-11-11 3:27 ` [Qemu-devel] [Qemu-ppc] " Alexey Kardashevskiy
2015-11-11 3:38 ` Benjamin Herrenschmidt
2015-11-11 4:07 ` Alexey Kardashevskiy
2015-11-11 4:16 ` Benjamin Herrenschmidt
2015-11-11 4:41 ` Alexey Kardashevskiy
2015-11-11 4:47 ` Benjamin Herrenschmidt
2015-11-27 10:21 ` Alexander Graf
2015-11-28 7:59 ` Benjamin Herrenschmidt
2015-11-28 10:53 ` Alexander Graf
2015-11-29 0:38 ` Benjamin Herrenschmidt
2015-11-30 18:15 ` Cédric Le Goater
2015-11-30 20:09 ` Benjamin Herrenschmidt
2015-11-30 21:24 ` Cédric Le Goater
2015-11-30 23:12 ` Benjamin Herrenschmidt
2015-12-07 1:25 ` Stewart Smith
2015-12-07 22:48 ` Cédric Le Goater
2015-11-11 0:57 ` Stewart Smith
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