From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: Re: [PATCH 2/9] xen/arm: vgic-v3: Only emulate identification registers requested by the spec Date: Mon, 16 Nov 2015 13:27:36 +0000 Message-ID: <1447680456.27871.89.camel@citrix.com> References: <1447415672-31633-1-git-send-email-julien.grall@citrix.com> <1447415672-31633-3-git-send-email-julien.grall@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1ZyJpF-0000XJ-9v for xen-devel@lists.xenproject.org; Mon, 16 Nov 2015 13:28:05 +0000 In-Reply-To: <1447415672-31633-3-git-send-email-julien.grall@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Julien Grall , xen-devel@lists.xenproject.org Cc: stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org On Fri, 2015-11-13 at 11:54 +0000, Julien Grall wrote: > Most of the identification registers space contains implementation > defined registers (see 8.1.13 in ARM IHI 0069A) and only GIC{D,R}_PIDR2 > is required to be implemented. I think you mean s/requested/required/ in the subject too? > > Currently the emulation of those registers mimic the ARM implementation, > but it's untrue to say that we properly emulate a such implementation. > > Keep only GIC{D,R}_PIDR2 implemented with the "implementationd defined "implementation" > bits" to zero and the ArchRev field (bits[7:4]) to 0x3 as we emulate a > GICv3. > > Note that the emulation of the range wasn't valid anyway because the > registers are split in 2 sets (PIDR4-PIDR7 and PIDR0-PIDR2). > > Signed-off-by: Julien Grall Acked-by: Ian Campbell