diff for duplicates of <1447809149-29724-3-git-send-email-sboyd@codeaurora.org> diff --git a/a/1.txt b/N1/1.txt index a1cdd83..55be5d0 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -80,7 +80,7 @@ index 000000000000..9bab5c011c07 + }; + + soc { -+ serial@75b0000 { ++ serial at 75b0000 { + status = "okay"; + }; + }; @@ -127,7 +127,7 @@ index 000000000000..cf5d361283de + #address-cells = <2>; + #size-cells = <0>; + -+ CPU0: cpu@0 { ++ CPU0: cpu at 0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; @@ -139,7 +139,7 @@ index 000000000000..cf5d361283de + }; + }; + -+ CPU1: cpu@1 { ++ CPU1: cpu at 1 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x1>; @@ -147,7 +147,7 @@ index 000000000000..cf5d361283de + next-level-cache = <&L2_0>; + }; + -+ CPU2: cpu@100 { ++ CPU2: cpu at 100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; @@ -159,7 +159,7 @@ index 000000000000..cf5d361283de + }; + }; + -+ CPU3: cpu@101 { ++ CPU3: cpu at 101 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x101>; @@ -225,7 +225,7 @@ index 000000000000..cf5d361283de + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + -+ intc: interrupt-controller@9bc0000 { ++ intc: interrupt-controller at 9bc0000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; @@ -236,14 +236,14 @@ index 000000000000..cf5d361283de + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + -+ gcc: clock-controller@300000 { ++ gcc: clock-controller at 300000 { + compatible = "qcom,gcc-msm8996"; + #clock-cells = <1>; + #reset-cells = <1>; + reg = <0x300000 0x90000>; + }; + -+ blsp2_uart1: serial@75b0000 { ++ blsp2_uart1: serial at 75b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x75b0000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; @@ -253,7 +253,7 @@ index 000000000000..cf5d361283de + status = "disabled"; + }; + -+ pinctrl@1010000 { ++ pinctrl at 1010000 { + compatible = "qcom,msm8996-pinctrl"; + reg = <0x01010000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; @@ -263,7 +263,7 @@ index 000000000000..cf5d361283de + #interrupt-cells = <2>; + }; + -+ timer@09840000 { ++ timer at 09840000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; @@ -271,7 +271,7 @@ index 000000000000..cf5d361283de + reg = <0x09840000 0x1000>; + clock-frequency = <19200000>; + -+ frame@9850000 { ++ frame at 9850000 { + frame-number = <0>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; @@ -279,42 +279,42 @@ index 000000000000..cf5d361283de + <0x09860000 0x1000>; + }; + -+ frame@9870000 { ++ frame at 9870000 { + frame-number = <1>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x09870000 0x1000>; + status = "disabled"; + }; + -+ frame@9880000 { ++ frame at 9880000 { + frame-number = <2>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x09880000 0x1000>; + status = "disabled"; + }; + -+ frame@9890000 { ++ frame at 9890000 { + frame-number = <3>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x09890000 0x1000>; + status = "disabled"; + }; + -+ frame@98a0000 { ++ frame at 98a0000 { + frame-number = <4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x098a0000 0x1000>; + status = "disabled"; + }; + -+ frame@98b0000 { ++ frame at 98b0000 { + frame-number = <5>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x098b0000 0x1000>; + status = "disabled"; + }; + -+ frame@98c0000 { ++ frame at 98c0000 { + frame-number = <6>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x098c0000 0x1000>; @@ -322,7 +322,7 @@ index 000000000000..cf5d361283de + }; + }; + -+ spmi_bus: qcom,spmi@400f000 { ++ spmi_bus: qcom,spmi at 400f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x400f000 0x1000>, + <0x4400000 0x800000>, @@ -340,7 +340,7 @@ index 000000000000..cf5d361283de + #interrupt-cells = <4>; + }; + -+ mmcc: clock-controller@8c0000 { ++ mmcc: clock-controller at 8c0000 { + compatible = "qcom,mmcc-msm8996"; + #clock-cells = <1>; + #reset-cells = <1>; diff --git a/a/content_digest b/N1/content_digest index 8585fc0..bc8ae0b 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,11 +1,8 @@ "ref\01447809149-29724-1-git-send-email-sboyd@codeaurora.org\0" - "From\0Stephen Boyd <sboyd@codeaurora.org>\0" + "From\0sboyd@codeaurora.org (Stephen Boyd)\0" "Subject\0[PATCH 2/4] arm64: dts: Add msm8996 SoC and MTP board support\0" "Date\0Tue, 17 Nov 2015 17:12:27 -0800\0" - "To\0Andy Gross <agross@codeaurora.org>\0" - "Cc\0linux-kernel@vger.kernel.org" - linux-arm-msm@vger.kernel.org - " linux-arm-kernel@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Add initial device tree support for the Qualcomm MSM8996 SoC and\n" @@ -90,7 +87,7 @@ "+\t};\n" "+\n" "+\tsoc {\n" - "+\t\tserial@75b0000 {\n" + "+\t\tserial at 75b0000 {\n" "+\t\t\tstatus = \"okay\";\n" "+\t\t};\n" "+\t};\n" @@ -137,7 +134,7 @@ "+\t\t#address-cells = <2>;\n" "+\t\t#size-cells = <0>;\n" "+\n" - "+\t\tCPU0: cpu@0 {\n" + "+\t\tCPU0: cpu at 0 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"qcom,kryo\";\n" "+\t\t\treg = <0x0 0x0>;\n" @@ -149,7 +146,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tCPU1: cpu@1 {\n" + "+\t\tCPU1: cpu at 1 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"qcom,kryo\";\n" "+\t\t\treg = <0x0 0x1>;\n" @@ -157,7 +154,7 @@ "+\t\t\tnext-level-cache = <&L2_0>;\n" "+\t\t};\n" "+\n" - "+\t\tCPU2: cpu@100 {\n" + "+\t\tCPU2: cpu at 100 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"qcom,kryo\";\n" "+\t\t\treg = <0x0 0x100>;\n" @@ -169,7 +166,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tCPU3: cpu@101 {\n" + "+\t\tCPU3: cpu at 101 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"qcom,kryo\";\n" "+\t\t\treg = <0x0 0x101>;\n" @@ -235,7 +232,7 @@ "+\t\tranges = <0 0 0 0xffffffff>;\n" "+\t\tcompatible = \"simple-bus\";\n" "+\n" - "+\t\tintc: interrupt-controller@9bc0000 {\n" + "+\t\tintc: interrupt-controller at 9bc0000 {\n" "+\t\t\tcompatible = \"arm,gic-v3\";\n" "+\t\t\t#interrupt-cells = <3>;\n" "+\t\t\tinterrupt-controller;\n" @@ -246,14 +243,14 @@ "+\t\t\tinterrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t};\n" "+\n" - "+\t\tgcc: clock-controller@300000 {\n" + "+\t\tgcc: clock-controller at 300000 {\n" "+\t\t\tcompatible = \"qcom,gcc-msm8996\";\n" "+\t\t\t#clock-cells = <1>;\n" "+\t\t\t#reset-cells = <1>;\n" "+\t\t\treg = <0x300000 0x90000>;\n" "+\t\t};\n" "+\n" - "+\t\tblsp2_uart1: serial@75b0000 {\n" + "+\t\tblsp2_uart1: serial at 75b0000 {\n" "+\t\t\tcompatible = \"qcom,msm-uartdm-v1.4\", \"qcom,msm-uartdm\";\n" "+\t\t\treg = <0x75b0000 0x1000>;\n" "+\t\t\tinterrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -263,7 +260,7 @@ "+\t\t\tstatus = \"disabled\";\n" "+\t\t};\n" "+\n" - "+\t\tpinctrl@1010000 {\n" + "+\t\tpinctrl at 1010000 {\n" "+\t\t\tcompatible = \"qcom,msm8996-pinctrl\";\n" "+\t\t\treg = <0x01010000 0x300000>;\n" "+\t\t\tinterrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -273,7 +270,7 @@ "+\t\t\t#interrupt-cells = <2>;\n" "+\t\t};\n" "+\n" - "+\t\ttimer@09840000 {\n" + "+\t\ttimer at 09840000 {\n" "+\t\t\t#address-cells = <1>;\n" "+\t\t\t#size-cells = <1>;\n" "+\t\t\tranges;\n" @@ -281,7 +278,7 @@ "+\t\t\treg = <0x09840000 0x1000>;\n" "+\t\t\tclock-frequency = <19200000>;\n" "+\n" - "+\t\t\tframe@9850000 {\n" + "+\t\t\tframe at 9850000 {\n" "+\t\t\t\tframe-number = <0>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,\n" "+\t\t\t\t\t <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -289,42 +286,42 @@ "+\t\t\t\t <0x09860000 0x1000>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tframe@9870000 {\n" + "+\t\t\tframe at 9870000 {\n" "+\t\t\t\tframe-number = <1>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t\t\treg = <0x09870000 0x1000>;\n" "+\t\t\t\tstatus = \"disabled\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tframe@9880000 {\n" + "+\t\t\tframe at 9880000 {\n" "+\t\t\t\tframe-number = <2>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t\t\treg = <0x09880000 0x1000>;\n" "+\t\t\t\tstatus = \"disabled\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tframe@9890000 {\n" + "+\t\t\tframe at 9890000 {\n" "+\t\t\t\tframe-number = <3>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t\t\treg = <0x09890000 0x1000>;\n" "+\t\t\t\tstatus = \"disabled\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tframe@98a0000 {\n" + "+\t\t\tframe at 98a0000 {\n" "+\t\t\t\tframe-number = <4>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t\t\treg = <0x098a0000 0x1000>;\n" "+\t\t\t\tstatus = \"disabled\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tframe@98b0000 {\n" + "+\t\t\tframe at 98b0000 {\n" "+\t\t\t\tframe-number = <5>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t\t\treg = <0x098b0000 0x1000>;\n" "+\t\t\t\tstatus = \"disabled\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tframe@98c0000 {\n" + "+\t\t\tframe at 98c0000 {\n" "+\t\t\t\tframe-number = <6>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;\n" "+\t\t\t\treg = <0x098c0000 0x1000>;\n" @@ -332,7 +329,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tspmi_bus: qcom,spmi@400f000 {\n" + "+\t\tspmi_bus: qcom,spmi at 400f000 {\n" "+\t\t\tcompatible = \"qcom,spmi-pmic-arb\";\n" "+\t\t\treg = <0x400f000 0x1000>,\n" "+\t\t\t <0x4400000 0x800000>,\n" @@ -350,7 +347,7 @@ "+\t\t\t#interrupt-cells = <4>;\n" "+\t\t};\n" "+\n" - "+\t\tmmcc: clock-controller@8c0000 {\n" + "+\t\tmmcc: clock-controller at 8c0000 {\n" "+\t\t\tcompatible = \"qcom,mmcc-msm8996\";\n" "+\t\t\t#clock-cells = <1>;\n" "+\t\t\t#reset-cells = <1>;\n" @@ -372,4 +369,4 @@ "The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\n" a Linux Foundation Collaborative Project -247bec281785f8be811f2be1b6ac3300e7df6a93ebafc98e1cf4e9d1a711eb59 +ccc29c7f2c88b1287d815fdf7804068aa7e8841904150ba50bb35cda21e03fe5
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