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From: Deepak M <m.deepak@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Deepak M <m.deepak@intel.com>, Jani Nikula <jani.nikula@intel.com>
Subject: [MIPI SEQ PARSING v3 08/13] drm/i915: Extend gpio read/write to other cores
Date: Tue,  1 Dec 2015 04:17:11 +0530	[thread overview]
Message-ID: <1448923632-16760-9-git-send-email-m.deepak@intel.com> (raw)
In-Reply-To: <1448923632-16760-1-git-send-email-m.deepak@intel.com>

Adding a argument to the gpio read/write functions
which accepts the block name.

v2: rebase
v3: rebase

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Deepak M <m.deepak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h            | 5 +++--
 drivers/gpu/drm/i915/i915_reg.h            | 5 +++++
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 4 ++--
 drivers/gpu/drm/i915/intel_sideband.c      | 9 +++++----
 4 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 59a39d1..ca865f4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3379,8 +3379,9 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val
 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
-u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
-void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 vlv_gpio_read(struct drm_i915_private *dev_priv, u8 core_offset, u32 reg);
+void vlv_gpio_write(struct drm_i915_private *dev_priv, u8 core_offset,
+			u32 reg, u32 val);
 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8bd2699..e29f7ef 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -572,6 +572,11 @@
 #define   IOSF_PORT_DPIO			0x12
 #define   IOSF_PORT_DPIO_2			0x1a
 #define   IOSF_PORT_GPIO_NC			0x13
+#define   IOSF_PORT_GPIO_SC			0x48
+#define   IOSF_PORT_GPIO_SUS			0xA8
+#define   MAX_GPIO_NUM_NC			26
+#define   MAX_GPIO_NUM_SC			128
+#define   MAX_GPIO_NUM				172
 #define   IOSF_PORT_CCK				0x14
 #define   IOSF_PORT_CCU				0xA9
 #define   IOSF_PORT_GPS_CORE			0x48
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index eb0697b..bc33e3a 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -275,14 +275,14 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 	if (!gtable[gpio].init) {
 		/* program the function */
 		/* FIXME: remove constant below */
-		vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
+		vlv_gpio_write(dev_priv, IOSF_PORT_GPIO_NC, function, 0x2000CC00);
 		gtable[gpio].init = 1;
 	}
 
 	val = 0x4 | action;
 
 	/* pull up/down */
-	vlv_gpio_nc_write(dev_priv, pad, val);
+	vlv_gpio_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
 	mutex_unlock(&dev_priv->sb_lock);
 
 	return data;
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 8831fc5..3e0cbe6 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -129,17 +129,18 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
 	return val;
 }
 
-u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
+u32 vlv_gpio_read(struct drm_i915_private *dev_priv, u8 core_offset, u32 reg)
 {
 	u32 val = 0;
-	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
+	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), core_offset,
 			SB_CRRDDA_NP, reg, &val);
 	return val;
 }
 
-void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+void vlv_gpio_write(struct drm_i915_private *dev_priv, u8 core_offset,
+				u32 reg, u32 val)
 {
-	vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
+	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), core_offset,
 			SB_CRWRDA_NP, reg, &val);
 }
 
-- 
1.9.1

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  parent reply	other threads:[~2015-11-30 17:13 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-30 22:47 [MIPI SEQ PARSING v3 00/13] Patches to support the version 3 of MIPI sequence in VBT Deepak M
2015-11-30 22:47 ` [MIPI SEQ PARSING v3 01/13] drm/i915: Adding the parsing logic for the i2c element Deepak M
2015-12-11  8:40   ` Mika Kahola
2015-11-30 22:47 ` [MIPI SEQ PARSING v3 02/13] drm/i915: Updating asle structure with new fields Deepak M
2015-12-11  8:41   ` Mika Kahola
2015-12-14 11:02   ` Jani Nikula
2015-11-30 22:47 ` [MIPI SEQ PARSING v3 03/13] drm/i915: Add Intel opregion mailbox 5 structure Deepak M
2015-12-11  8:42   ` Mika Kahola
2015-11-30 22:47 ` [MIPI SEQ PARSING v3 04/13] drm/i915: Do opregion VBT validation during opregion setup Deepak M
2015-12-11  8:43   ` Mika Kahola
2015-11-30 22:47 ` [MIPI SEQ PARSING v3 05/13] drm/i915: Add debug entry to get the opregion VBT blob Deepak M
2015-12-11  8:46   ` Mika Kahola
2015-12-14 12:16     ` [PATCH] drm/i915: Parsing VBT if size of VBT exceeds 6KB Deepak M
2015-12-14  9:19       ` Chris Wilson
2015-12-14 10:56         ` Jani Nikula
2015-11-30 22:47 ` [MIPI SEQ PARSING v3 06/13] " Deepak M
2015-12-11  8:51   ` Mika Kahola
2015-11-30 22:47 ` [MIPI SEQ PARSING v3 07/13] drm/i915: Added support the v3 mipi sequence block Deepak M
2015-11-30 22:47 ` Deepak M [this message]
2015-12-15 19:53   ` [MIPI SEQ PARSING v3 08/13] drm/i915: Extend gpio read/write to other cores Ville Syrjälä
2015-11-30 22:47 ` [MIPI SEQ PARSING v3 09/13] drm/i915: Added the generic gpio sequence support and gpio table Deepak M
2015-12-15 20:05   ` Ville Syrjälä

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