diff for duplicates of <1449047797-4300-1-git-send-email-linux-kernel-dev@beckhoff.com> diff --git a/a/1.txt b/N1/1.txt index 2d5ade8..5996f03 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,4 +1,4 @@ -From: Patrick Br=C3=BCnn <p.bruenn@beckhoff.com> +From: Patrick Br?nn <p.bruenn@beckhoff.com> To obtain exact pixel clocks, allow the DI clock selectors to influence the PLLs that they are derived from. @@ -8,45 +8,31 @@ rates") did this for i.MX6. Port it to enable high display resolutions on i.MX53 based platforms such as CX9020 Embedded PC, too. -Signed-off-by: Patrick Br=C3=BCnn <p.bruenn@beckhoff.com> +Signed-off-by: Patrick Br?nn <p.bruenn@beckhoff.com> --- v2: add clk maintainers to CC and fix commit message format drivers/clk/imx/clk-imx51-imx53.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -diff --git a/drivers/clk/imx/clk-imx51-imx53.c b/drivers/clk/imx/clk-imx51-= -imx53.c +diff --git a/drivers/clk/imx/clk-imx51-imx53.c b/drivers/clk/imx/clk-imx51-imx53.c index c677034..29d4c44 100644 --- a/drivers/clk/imx/clk-imx51-imx53.c +++ b/drivers/clk/imx/clk-imx51-imx53.c -@@ -519,10 +519,10 @@ static void __init mx53_clocks_init(struct device_nod= -e *np) - mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT)= -; - clk[IMX5_CLK_LDB_DI0_GATE] =3D imx_clk_gate2("ldb_di0_gate", "ldb_di0_div= -", MXC_CCM_CCGR6, 28); - clk[IMX5_CLK_LDB_DI1_GATE] =3D imx_clk_gate2("ldb_di1_gate", "ldb_di1_div= -", MXC_CCM_CCGR6, 30); -- clk[IMX5_CLK_IPU_DI0_SEL] =3D imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, = -26, 3, +@@ -519,10 +519,10 @@ static void __init mx53_clocks_init(struct device_node *np) + mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT); + clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28); + clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30); +- clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, - mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel)); -- clk[IMX5_CLK_IPU_DI1_SEL] =3D imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, = -29, 3, +- clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, - mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel)); -+ clk[IMX5_CLK_IPU_DI0_SEL] =3D imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CS= -CMR2, 26, 3, -+ mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel), CLK_SET_RATE_PARENT)= -; -+ clk[IMX5_CLK_IPU_DI1_SEL] =3D imx_clk_mux_flags("ipu_di1_sel", MXC_CCM_CS= -CMR2, 29, 3, -+ mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel), CLK_SET_RATE_PARENT)= -; - clk[IMX5_CLK_TVE_EXT_SEL] =3D imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CS= -CMR1, 6, 1, - mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT)= -; - clk[IMX5_CLK_TVE_GATE] =3D imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM= -_CCGR2, 30); ---=20 ++ clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, ++ mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel), CLK_SET_RATE_PARENT); ++ clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux_flags("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, ++ mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel), CLK_SET_RATE_PARENT); + clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, + mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT); + clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30); +-- 1.9.1 diff --git a/a/content_digest b/N1/content_digest index e5e6165..277c695 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,17 +1,10 @@ - "From\0<linux-kernel-dev@beckhoff.com>\0" + "From\0linux-kernel-dev@beckhoff.com (linux-kernel-dev at beckhoff.com)\0" "Subject\0[PATCH v2] clk: imx5: ipu_di_sel clocks can set parent rates\0" "Date\0Wed, 2 Dec 2015 10:16:37 +0100\0" - "To\0<shawnguo@kernel.org>" - " <kernel@pengutronix.de>\0" - "Cc\0mturquette@baylibre.com" - sboyd@codeaurora.org - linux-arm-kernel@lists.infradead.org - linux-clk@vger.kernel.org - linux-kernel@vger.kernel.org - " Patrick Br\303\274nn <p.bruenn@beckhoff.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" - "From: Patrick Br=C3=BCnn <p.bruenn@beckhoff.com>\n" + "From: Patrick Br?nn <p.bruenn@beckhoff.com>\n" "\n" "To obtain exact pixel clocks, allow the DI clock selectors to influence\n" "the PLLs that they are derived from.\n" @@ -21,47 +14,33 @@ "Port it to enable high display resolutions on i.MX53 based platforms\n" "such as CX9020 Embedded PC, too.\n" "\n" - "Signed-off-by: Patrick Br=C3=BCnn <p.bruenn@beckhoff.com>\n" + "Signed-off-by: Patrick Br?nn <p.bruenn@beckhoff.com>\n" "---\n" "v2: add clk maintainers to CC and fix commit message format\n" "\n" " drivers/clk/imx/clk-imx51-imx53.c | 8 ++++----\n" " 1 file changed, 4 insertions(+), 4 deletions(-)\n" "\n" - "diff --git a/drivers/clk/imx/clk-imx51-imx53.c b/drivers/clk/imx/clk-imx51-=\n" - "imx53.c\n" + "diff --git a/drivers/clk/imx/clk-imx51-imx53.c b/drivers/clk/imx/clk-imx51-imx53.c\n" "index c677034..29d4c44 100644\n" "--- a/drivers/clk/imx/clk-imx51-imx53.c\n" "+++ b/drivers/clk/imx/clk-imx51-imx53.c\n" - "@@ -519,10 +519,10 @@ static void __init mx53_clocks_init(struct device_nod=\n" - "e *np)\n" - " \t\t\t\t\t\tmx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT)=\n" - ";\n" - " \tclk[IMX5_CLK_LDB_DI0_GATE]\t=3D imx_clk_gate2(\"ldb_di0_gate\", \"ldb_di0_div=\n" - "\", MXC_CCM_CCGR6, 28);\n" - " \tclk[IMX5_CLK_LDB_DI1_GATE]\t=3D imx_clk_gate2(\"ldb_di1_gate\", \"ldb_di1_div=\n" - "\", MXC_CCM_CCGR6, 30);\n" - "-\tclk[IMX5_CLK_IPU_DI0_SEL]\t=3D imx_clk_mux(\"ipu_di0_sel\", MXC_CCM_CSCMR2, =\n" - "26, 3,\n" + "@@ -519,10 +519,10 @@ static void __init mx53_clocks_init(struct device_node *np)\n" + " \t\t\t\t\t\tmx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);\n" + " \tclk[IMX5_CLK_LDB_DI0_GATE]\t= imx_clk_gate2(\"ldb_di0_gate\", \"ldb_di0_div\", MXC_CCM_CCGR6, 28);\n" + " \tclk[IMX5_CLK_LDB_DI1_GATE]\t= imx_clk_gate2(\"ldb_di1_gate\", \"ldb_di1_div\", MXC_CCM_CCGR6, 30);\n" + "-\tclk[IMX5_CLK_IPU_DI0_SEL]\t= imx_clk_mux(\"ipu_di0_sel\", MXC_CCM_CSCMR2, 26, 3,\n" "-\t\t\t\t\t\tmx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));\n" - "-\tclk[IMX5_CLK_IPU_DI1_SEL]\t=3D imx_clk_mux(\"ipu_di1_sel\", MXC_CCM_CSCMR2, =\n" - "29, 3,\n" + "-\tclk[IMX5_CLK_IPU_DI1_SEL]\t= imx_clk_mux(\"ipu_di1_sel\", MXC_CCM_CSCMR2, 29, 3,\n" "-\t\t\t\t\t\tmx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));\n" - "+\tclk[IMX5_CLK_IPU_DI0_SEL]\t=3D imx_clk_mux_flags(\"ipu_di0_sel\", MXC_CCM_CS=\n" - "CMR2, 26, 3,\n" - "+\t\t\t\t\t\tmx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel), CLK_SET_RATE_PARENT)=\n" - ";\n" - "+\tclk[IMX5_CLK_IPU_DI1_SEL]\t=3D imx_clk_mux_flags(\"ipu_di1_sel\", MXC_CCM_CS=\n" - "CMR2, 29, 3,\n" - "+\t\t\t\t\t\tmx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel), CLK_SET_RATE_PARENT)=\n" - ";\n" - " \tclk[IMX5_CLK_TVE_EXT_SEL]\t=3D imx_clk_mux_flags(\"tve_ext_sel\", MXC_CCM_CS=\n" - "CMR1, 6, 1,\n" - " \t\t\t\t\t\tmx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT)=\n" - ";\n" - " \tclk[IMX5_CLK_TVE_GATE]\t\t=3D imx_clk_gate2(\"tve_gate\", \"tve_pred\", MXC_CCM=\n" - "_CCGR2, 30);\n" - "--=20\n" + "+\tclk[IMX5_CLK_IPU_DI0_SEL]\t= imx_clk_mux_flags(\"ipu_di0_sel\", MXC_CCM_CSCMR2, 26, 3,\n" + "+\t\t\t\t\t\tmx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel), CLK_SET_RATE_PARENT);\n" + "+\tclk[IMX5_CLK_IPU_DI1_SEL]\t= imx_clk_mux_flags(\"ipu_di1_sel\", MXC_CCM_CSCMR2, 29, 3,\n" + "+\t\t\t\t\t\tmx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel), CLK_SET_RATE_PARENT);\n" + " \tclk[IMX5_CLK_TVE_EXT_SEL]\t= imx_clk_mux_flags(\"tve_ext_sel\", MXC_CCM_CSCMR1, 6, 1,\n" + " \t\t\t\t\t\tmx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);\n" + " \tclk[IMX5_CLK_TVE_GATE]\t\t= imx_clk_gate2(\"tve_gate\", \"tve_pred\", MXC_CCM_CCGR2, 30);\n" + "-- \n" 1.9.1 -fa4a8cda3f41b78e22180e1bfc9034197054a3ab36ca173750ae124cee57b114 +3e3613b7fa389f7ae31ee1865d04688fcb57799c6cc8702c6888c5735e12344c
diff --git a/a/1.txt b/N2/1.txt index 2d5ade8..6cb03f7 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,4 +1,4 @@ -From: Patrick Br=C3=BCnn <p.bruenn@beckhoff.com> +From: Patrick Brünn <p.bruenn@beckhoff.com> To obtain exact pixel clocks, allow the DI clock selectors to influence the PLLs that they are derived from. @@ -8,45 +8,31 @@ rates") did this for i.MX6. Port it to enable high display resolutions on i.MX53 based platforms such as CX9020 Embedded PC, too. -Signed-off-by: Patrick Br=C3=BCnn <p.bruenn@beckhoff.com> +Signed-off-by: Patrick Brünn <p.bruenn@beckhoff.com> --- v2: add clk maintainers to CC and fix commit message format drivers/clk/imx/clk-imx51-imx53.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -diff --git a/drivers/clk/imx/clk-imx51-imx53.c b/drivers/clk/imx/clk-imx51-= -imx53.c +diff --git a/drivers/clk/imx/clk-imx51-imx53.c b/drivers/clk/imx/clk-imx51-imx53.c index c677034..29d4c44 100644 --- a/drivers/clk/imx/clk-imx51-imx53.c +++ b/drivers/clk/imx/clk-imx51-imx53.c -@@ -519,10 +519,10 @@ static void __init mx53_clocks_init(struct device_nod= -e *np) - mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT)= -; - clk[IMX5_CLK_LDB_DI0_GATE] =3D imx_clk_gate2("ldb_di0_gate", "ldb_di0_div= -", MXC_CCM_CCGR6, 28); - clk[IMX5_CLK_LDB_DI1_GATE] =3D imx_clk_gate2("ldb_di1_gate", "ldb_di1_div= -", MXC_CCM_CCGR6, 30); -- clk[IMX5_CLK_IPU_DI0_SEL] =3D imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, = -26, 3, +@@ -519,10 +519,10 @@ static void __init mx53_clocks_init(struct device_node *np) + mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT); + clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28); + clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30); +- clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, - mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel)); -- clk[IMX5_CLK_IPU_DI1_SEL] =3D imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, = -29, 3, +- clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, - mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel)); -+ clk[IMX5_CLK_IPU_DI0_SEL] =3D imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CS= -CMR2, 26, 3, -+ mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel), CLK_SET_RATE_PARENT)= -; -+ clk[IMX5_CLK_IPU_DI1_SEL] =3D imx_clk_mux_flags("ipu_di1_sel", MXC_CCM_CS= -CMR2, 29, 3, -+ mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel), CLK_SET_RATE_PARENT)= -; - clk[IMX5_CLK_TVE_EXT_SEL] =3D imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CS= -CMR1, 6, 1, - mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT)= -; - clk[IMX5_CLK_TVE_GATE] =3D imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM= -_CCGR2, 30); ---=20 ++ clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, ++ mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel), CLK_SET_RATE_PARENT); ++ clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux_flags("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, ++ mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel), CLK_SET_RATE_PARENT); + clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, + mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT); + clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30); +-- 1.9.1 diff --git a/a/content_digest b/N2/content_digest index e5e6165..616fab3 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -11,7 +11,7 @@ " Patrick Br\303\274nn <p.bruenn@beckhoff.com>\0" "\00:1\0" "b\0" - "From: Patrick Br=C3=BCnn <p.bruenn@beckhoff.com>\n" + "From: Patrick Br\303\274nn <p.bruenn@beckhoff.com>\n" "\n" "To obtain exact pixel clocks, allow the DI clock selectors to influence\n" "the PLLs that they are derived from.\n" @@ -21,47 +21,33 @@ "Port it to enable high display resolutions on i.MX53 based platforms\n" "such as CX9020 Embedded PC, too.\n" "\n" - "Signed-off-by: Patrick Br=C3=BCnn <p.bruenn@beckhoff.com>\n" + "Signed-off-by: Patrick Br\303\274nn <p.bruenn@beckhoff.com>\n" "---\n" "v2: add clk maintainers to CC and fix commit message format\n" "\n" " drivers/clk/imx/clk-imx51-imx53.c | 8 ++++----\n" " 1 file changed, 4 insertions(+), 4 deletions(-)\n" "\n" - "diff --git a/drivers/clk/imx/clk-imx51-imx53.c b/drivers/clk/imx/clk-imx51-=\n" - "imx53.c\n" + "diff --git a/drivers/clk/imx/clk-imx51-imx53.c b/drivers/clk/imx/clk-imx51-imx53.c\n" "index c677034..29d4c44 100644\n" "--- a/drivers/clk/imx/clk-imx51-imx53.c\n" "+++ b/drivers/clk/imx/clk-imx51-imx53.c\n" - "@@ -519,10 +519,10 @@ static void __init mx53_clocks_init(struct device_nod=\n" - "e *np)\n" - " \t\t\t\t\t\tmx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT)=\n" - ";\n" - " \tclk[IMX5_CLK_LDB_DI0_GATE]\t=3D imx_clk_gate2(\"ldb_di0_gate\", \"ldb_di0_div=\n" - "\", MXC_CCM_CCGR6, 28);\n" - " \tclk[IMX5_CLK_LDB_DI1_GATE]\t=3D imx_clk_gate2(\"ldb_di1_gate\", \"ldb_di1_div=\n" - "\", MXC_CCM_CCGR6, 30);\n" - "-\tclk[IMX5_CLK_IPU_DI0_SEL]\t=3D imx_clk_mux(\"ipu_di0_sel\", MXC_CCM_CSCMR2, =\n" - "26, 3,\n" + "@@ -519,10 +519,10 @@ static void __init mx53_clocks_init(struct device_node *np)\n" + " \t\t\t\t\t\tmx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);\n" + " \tclk[IMX5_CLK_LDB_DI0_GATE]\t= imx_clk_gate2(\"ldb_di0_gate\", \"ldb_di0_div\", MXC_CCM_CCGR6, 28);\n" + " \tclk[IMX5_CLK_LDB_DI1_GATE]\t= imx_clk_gate2(\"ldb_di1_gate\", \"ldb_di1_div\", MXC_CCM_CCGR6, 30);\n" + "-\tclk[IMX5_CLK_IPU_DI0_SEL]\t= imx_clk_mux(\"ipu_di0_sel\", MXC_CCM_CSCMR2, 26, 3,\n" "-\t\t\t\t\t\tmx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));\n" - "-\tclk[IMX5_CLK_IPU_DI1_SEL]\t=3D imx_clk_mux(\"ipu_di1_sel\", MXC_CCM_CSCMR2, =\n" - "29, 3,\n" + "-\tclk[IMX5_CLK_IPU_DI1_SEL]\t= imx_clk_mux(\"ipu_di1_sel\", MXC_CCM_CSCMR2, 29, 3,\n" "-\t\t\t\t\t\tmx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));\n" - "+\tclk[IMX5_CLK_IPU_DI0_SEL]\t=3D imx_clk_mux_flags(\"ipu_di0_sel\", MXC_CCM_CS=\n" - "CMR2, 26, 3,\n" - "+\t\t\t\t\t\tmx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel), CLK_SET_RATE_PARENT)=\n" - ";\n" - "+\tclk[IMX5_CLK_IPU_DI1_SEL]\t=3D imx_clk_mux_flags(\"ipu_di1_sel\", MXC_CCM_CS=\n" - "CMR2, 29, 3,\n" - "+\t\t\t\t\t\tmx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel), CLK_SET_RATE_PARENT)=\n" - ";\n" - " \tclk[IMX5_CLK_TVE_EXT_SEL]\t=3D imx_clk_mux_flags(\"tve_ext_sel\", MXC_CCM_CS=\n" - "CMR1, 6, 1,\n" - " \t\t\t\t\t\tmx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT)=\n" - ";\n" - " \tclk[IMX5_CLK_TVE_GATE]\t\t=3D imx_clk_gate2(\"tve_gate\", \"tve_pred\", MXC_CCM=\n" - "_CCGR2, 30);\n" - "--=20\n" + "+\tclk[IMX5_CLK_IPU_DI0_SEL]\t= imx_clk_mux_flags(\"ipu_di0_sel\", MXC_CCM_CSCMR2, 26, 3,\n" + "+\t\t\t\t\t\tmx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel), CLK_SET_RATE_PARENT);\n" + "+\tclk[IMX5_CLK_IPU_DI1_SEL]\t= imx_clk_mux_flags(\"ipu_di1_sel\", MXC_CCM_CSCMR2, 29, 3,\n" + "+\t\t\t\t\t\tmx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel), CLK_SET_RATE_PARENT);\n" + " \tclk[IMX5_CLK_TVE_EXT_SEL]\t= imx_clk_mux_flags(\"tve_ext_sel\", MXC_CCM_CSCMR1, 6, 1,\n" + " \t\t\t\t\t\tmx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);\n" + " \tclk[IMX5_CLK_TVE_GATE]\t\t= imx_clk_gate2(\"tve_gate\", \"tve_pred\", MXC_CCM_CCGR2, 30);\n" + "-- \n" 1.9.1 -fa4a8cda3f41b78e22180e1bfc9034197054a3ab36ca173750ae124cee57b114 +70c4b511547396a5a54334bca94156990b7eb518b4ffe53838dca1e5ea229b90
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