[U-Boot] [PATCH] arm: socfpga: Fix cache configuration

[Chin Liang See <clsee@altera.com>]

On Tue, 2015-12-08 at 13:53 +0100, Marek Vasut wrote:
> On Tuesday, December 08, 2015 at 12:13:23 PM, Pavel Machek wrote:
> 
> [...]
> 
> > > > Thanks for the pointers.
> > > > 
> > > > I checked the source and enabled the debug message. Noticed my
> > > > failure
> > > > is due to small LEB and PEB size. It was set to 4k which is the
> > > > sub
> > > > -sector erase size of NOR flash. I suspect you didn't hit this
> > > > as you
> > > > generate ubinized image which is 64kB erase size.
> > > > 
> > > > I will continue to dig more. Need to ensure it works when user
> > > > create
> > > > UBI part in U-Boot on top of serial NOR flash (which is
> > > > commonly 4kB
> > > > erase size). Hopefully existing U-Boot already have source
> > > > taking care
> > > > this :)
> > > 
> > > I am tempted to revert this patch, since it breaks USB and UBI
> > > for me
> > > on two different boards though.
> > 
> > It caused regressions it was not supposed to change. That means
> > revert...
> 
> I found the bug, it's not a bug in this patch, but it's even broader
> issue.
> 

Nice!

> Look at arch/arm/lib/cache-cp15.c , the file checks for CONFIG_ARMV7
> and only
> ifdef CONFIG_ARMV7, then it configures TTBR0. If CONFIG_ARMV7 is not
> set, it 
> configures nothing. But, I cannot find any place for any ARMV7
> machine which 
> would actually set the CONFIG_ARMV7 option.
> 
> I verified this on SoCFPGA and indeed, CONFIG_ARMV7 is not set, so
> this piece
> of code is never executed and thus my cache misbehaves.
> 
> I guess the right way to fix this would be to replace #ifdef
> CONFIG_ARMV7 with
> CONFIG_CPU_V7 ? Or shall we add new symbol, CONFIG_ARMV7 and make
> CONFIG_CPU_V7
> select CONFIG_ARMV7 to avoid changing the system.h header, which is
> most likely
> taken from Linux ?
> 

I would opt for CONFIG_CPU_V7 as its specific to ARMV7 cache feature.

Thanks
Chin Liang

> Best regards,
> Marek Vasut