Re: [PATCH] dmaengine: dw: clear LLP_[SD]_EN bits in last descriptor of a chain

["Shevchenko, Andriy" <andriy.shevchenko@intel.com>]

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On Mon, 2015-12-21 at 21:34 +0200, Andy Shevchenko wrote:
> On Mon, 2015-12-21 at 19:10 +0000, Mans Rullgard wrote:
> > The datasheet requires that the LLP_[SD]_EN bits be cleared
> > whenever
> > LLP.LOC is zero, i.e. in the last descriptor of a multi-block
> > chain.
> > Make the driver do this.
> 
> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Vinod, I would like to postpone this patch for a while to make a bit
easier back porting of other dw_dmac changes wrt fix SATA on 460EX (*).

I will send it later in a bunch. Hope MÃ¥ns has no objections on this.

(*) Now I'm pretty sure that the main issues with SATA are a) wrong
master settings for transfers and LLP, and b) endiannes issue with
values in LLP. That's why I hope to have those patches coming first
with a proper Fixes: tag.

> 
> > 
> > Signed-off-by: Mans Rullgard <mans@mansr.com>
> > ---
> >  drivers/dma/dw/core.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
> > index 7067b6ddc1db..ca7cafc82f6b 100644
> > --- a/drivers/dma/dw/core.c
> > +++ b/drivers/dma/dw/core.c
> > @@ -751,6 +751,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan,
> > dma_addr_t dest, dma_addr_t src,
> >  		prev->lli.ctllo |= DWC_CTLL_INT_EN;
> >  
> >  	prev->lli.llp = 0;
> > +	prev->lli.ctllo &= ~(DWC_CTLL_LLP_D_EN |
> > DWC_CTLL_LLP_S_EN);
> >  	first->txd.flags = flags;
> >  	first->total_len = len;
> >  
> > @@ -912,6 +913,7 @@ slave_sg_fromdev_fill_desc:
> >  		prev->lli.ctllo |= DWC_CTLL_INT_EN;
> >  
> >  	prev->lli.llp = 0;
> > +	prev->lli.ctllo &= ~(DWC_CTLL_LLP_D_EN |
> > DWC_CTLL_LLP_S_EN);
> >  	first->total_len = total_len;
> >  
> >  	return &first->txd;
> 

-- 
Andy Shevchenko <andriy.shevchenko@intel.com>
Intel Finland Oy
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