From mboxrd@z Thu Jan 1 00:00:00 1970 From: marcel.ziswiler@toradex.com (Marcel Ziswiler) Date: Fri, 8 Jan 2016 08:28:58 +0000 Subject: [PATCH v2 1/2] ARM: dts: imx6: Add support for Toradex Apalis iMX6Q/D SoM In-Reply-To: <7e21f1c5e2e30fb2c7bfd9d47ba6e9d9@agner.ch> References: <1452011942-11940-1-git-send-email-marcel.ziswiler@toradex.com> <1452011942-11940-2-git-send-email-marcel.ziswiler@toradex.com> <7e21f1c5e2e30fb2c7bfd9d47ba6e9d9@agner.ch> Message-ID: <1452241735.3357.11.camel@toradex.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Stefan On Wed, 2016-01-06 at 22:29 -0800, Stefan Agner wrote: > Hi Marcel, > > On 2016-01-05 08:39, Marcel Ziswiler wrote: > > From: Petr ?tetiar > > > > Signed-off-by: Petr ?tetiar > > Signed-off-by: Marcel Ziswiler > > --- > > > > Changes in v2: > > - clarify exact Apalis iMX6Q/D SoM type in cover letter > > - clarify exact Apalis iMX6Q/D module type and Ixora carrier board > > in model > > ? node > > - got rid of obsolete mmc aliases > > - working SGTL5000 audio/sound integration > > - working STMPE811 touch screen controller integration > > - integrated review feedback from Lucas > > - left and even added some more comments as I don't see why putting > > any > > ? explanatory comments in dts' should be such a bad thing to do > > - completely got rid of the memory node as that is something > > typically filled > > ? in by the boot loader e.g. U-Boot > > - without the regulators simple-bus it no longer boots > > - even though we supposedly shipped a few hundred V1.0a modules > > drop DCE UART > > ? support for now and simplify file layout > > - replaced obsolete no-1-8-v by mainline supported voltage-ranges = > > <3300 3300> > > ? usdhc property and yes card detects are indeed active low (;-p) > > - integrated review feedback from Stefan > > - fixed Ethernet PHY reset & interrupt (requires Micrel PHY driver > > to be > > ? enabled) > > - fixed HDMI DDC (requires GPIO-based bitbanging I2C to be enabled) > > - fixed SPDIF > > > > ?arch/arm/boot/dts/imx6qdl-apalis.dtsi | 1040 > > +++++++++++++++++++++++++++++++++ > > ?1 file changed, 1040 insertions(+) > > ?create mode 100644 arch/arm/boot/dts/imx6qdl-apalis.dtsi > > > > diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi > > b/arch/arm/boot/dts/imx6qdl-apalis.dtsi > > new file mode 100644 > > index 0000000..6104e2e > > --- /dev/null > > +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi > > @@ -0,0 +1,1040 @@ > > +/* > > + * Copyright 2014-2016 Toradex AG > > + * Copyright 2012 Freescale Semiconductor, Inc. > > + * Copyright 2011 Linaro Ltd. > > + * > > + * This file is dual-licensed: you can use it either under the > > terms > > + * of the GPL or the X11 license, at your option. Note that this > > dual > > + * licensing only applies to this file, and not this project as a > > + * whole. > > + * > > + *??a) This file is free software; you can redistribute it and/or > > + *?????modify it under the terms of the GNU General Public License > > + *?????version 2 as published by the Free Software Foundation. > > + * > > + *?????This file is distributed in the hope that it will be useful > > + *?????but WITHOUT ANY WARRANTY; without even the implied warranty > > of > > + *?????MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.??See > > the > > + *?????GNU General Public License for more details. > > + * > > + * Or, alternatively > > + * > > + *??b) Permission is hereby granted, free of charge, to any person > > + *?????obtaining a copy of this software and associated > > documentation > > + *?????files (the "Software"), to deal in the Software without > > + *?????restriction, including without limitation the rights to use > > + *?????copy, modify, merge, publish, distribute, sublicense, > > and/or > > + *?????sell copies of the Software, and to permit persons to whom > > the > > + *?????Software is furnished to do so, subject to the following > > + *?????conditions: > > + * > > + *?????The above copyright notice and this permission notice shall > > be > > + *?????included in all copies or substantial portions of the > > Software. > > + * > > + *?????THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND > > + *?????EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE > > WARRANTIES > > + *?????OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > > + *?????NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > > + *?????HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY > > + *?????WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > > ARISING > > + *?????FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE > > OR > > + *?????OTHER DEALINGS IN THE SOFTWARE. > > + */ > > + > > +#include > > + > > +/ { > > + model = "Toradex Apalis iMX6Q/D Module"; > > + compatible = "toradex,apalis_imx6q", "fsl,imx6q"; > > + > > + backlight: backlight { > > + compatible = "pwm-backlight"; > > + pwms = <&pwm4 0 5000000>; > > + status = "disabled"; > > + }; > > + > > + /* DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 */ > > + i2cddc: i2c at 0 { > > + compatible = "i2c-gpio"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_i2c_ddc>; > > + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH /* sda */ > > + ?&gpio2 30 GPIO_ACTIVE_HIGH /* scl */ > > + >; > > + i2c-gpio,delay-us = <2>; /* ~100 kHz */ > > + status = "okay"; > > + }; > > + > > + regulators { > > + compatible = "simple-bus"; > > + > > + reg_1p8v: 1p8v { > > + compatible = "regulator-fixed"; > > + regulator-name = "1P8V"; > > + regulator-min-microvolt = <1800000>; > > + regulator-max-microvolt = <1800000>; > > + regulator-always-on; > > + }; > > + > > + reg_2p5v: 2p5v { > > + compatible = "regulator-fixed"; > > + regulator-name = "2P5V"; > > + regulator-min-microvolt = <2500000>; > > + regulator-max-microvolt = <2500000>; > > + regulator-always-on; > > + }; > > + > > + reg_3p3v: 3p3v { > > + compatible = "regulator-fixed"; > > + regulator-name = "3P3V"; > > + regulator-min-microvolt = <3300000>; > > + regulator-max-microvolt = <3300000>; > > + regulator-always-on; > > + }; > > + > > + reg_usb_otg_vbus: usb_otg_vbus { > > + compatible = "regulator-fixed"; > > + pinctrl-names = "default"; > > + pinctrl-0 = > > <&pinctrl_regulator_usbotg_pwr>; > > + regulator-name = "usb_otg_vbus"; > > + regulator-min-microvolt = <5000000>; > > + regulator-max-microvolt = <5000000>; > > + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; > > + enable-active-high; > > + status = "disabled"; > > + }; > > + > > + /* on module usb hub */ > > + reg_usb_host_vbus_hub: usb_host_vbus_hub { > > + compatible = "regulator-fixed"; > > + pinctrl-names = "default"; > > + pinctrl-0 = > > <&pinctrl_regulator_usbhub_pwr>; > > + regulator-name = "usb_host_vbus_hub"; > > + regulator-min-microvolt = <5000000>; > > + regulator-max-microvolt = <5000000>; > > + gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; > > + startup-delay-us = <2000>; > > + enable-active-high; > > + status = "okay"; > > + }; > > + > > + reg_usb_host_vbus: usb_host_vbus { > > + compatible = "regulator-fixed"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; > > + regulator-name = "usb_host_vbus"; > > + regulator-min-microvolt = <5000000>; > > + regulator-max-microvolt = <5000000>; > > + gpio =??<&gpio1 0 GPIO_ACTIVE_HIGH>; > > + enable-active-high; > > + vin-supply = <®_usb_host_vbus_hub>; > > + status = "disabled"; > > + }; > > + }; > > + > > + sound { > > + compatible = "fsl,imx-audio-sgtl5000"; > > + model = "imx6q-apalis-sgtl5000"; > > + ssi-controller = <&ssi1>; > > + audio-codec = <&codec>; > > + audio-routing = > > + "LINE_IN", "Line In Jack", > > + "MIC_IN", "Mic Jack", > > + "Mic Jack", "Mic Bias", > > + "Headphone Jack", "HP_OUT"; > > + mux-int-port = <1>; > > + mux-ext-port = <4>; > > + }; > > + > > + sound_spdif: sound-spdif { > > + compatible = "fsl,imx-audio-spdif"; > > + model = "imx-spdif"; > > + spdif-controller = <&spdif>; > > + spdif-in; > > + spdif-out; > > + status = "disabled"; > > + }; > > +}; > > + > > +&audmux { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_audmux &pinctrl_audmux_mclk>; > > + status = "okay"; > > +}; > > + > > +/* Apalis SPI1 */ > > +&ecspi1 { > > + fsl,spi-num-chipselects = <1>; > > + cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_spi_cs1>; > > + status = "disabled"; > > +}; > > + > > +/* Apalis SPI2 */ > > +&ecspi2 { > > + fsl,spi-num-chipselects = <1>; > > + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_spi_cs2>; > > + status = "disabled"; > > +}; > > + > > +&fec { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_enet &pinctrl_enet_ctrl>; > > + phy-mode = "rgmii"; > > + phy-handle = <ðphy>; > > + phy-reset-duration = <10>; > > + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; > > + status = "okay"; > > + > > + mdio { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + ethphy: ethernet-phy at 7 { > > + interrupt-parent = <&gpio1>; > > + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; > > + reg = <7>; > > + }; > > + }; > > +}; > > + > > +&can1 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_flexcan1>; > > + status = "disabled"; > > +}; > > + > > +&can2 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_flexcan2>; > > + status = "disabled"; > > +}; > > + > > +&hdmi { > > + ddc-i2c-bus = <&i2cddc>; > > + status = "okay"; > > +}; > > + > > +/* > > + * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier > > + * board) > > + */ > > +&i2c1 { > > + clock-frequency = <100000>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_i2c1>; > > + status = "disabled"; > > +}; > > + > > +&i2c2 { > > + clock-frequency = <100000>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_i2c2>; > > + status = "okay"; > > + > > + pmic: pfuze100 at 08 { > > + compatible = "fsl,pfuze100"; > > + reg = <0x08>; > > + > > + regulators { > > + sw1a_reg: sw1ab { > > + regulator-min-microvolt = > > <300000>; > > + regulator-max-microvolt = > > <1875000>; > > + regulator-boot-on; > > + regulator-always-on; > > + regulator-ramp-delay = <6250>; > > + }; > > + > > + sw1c_reg: sw1c { > > + regulator-min-microvolt = > > <300000>; > > + regulator-max-microvolt = > > <1875000>; > > + regulator-boot-on; > > + regulator-always-on; > > + regulator-ramp-delay = <6250>; > > + }; > > + > > + sw3a_reg: sw3a { > > + regulator-min-microvolt = > > <400000>; > > + regulator-max-microvolt = > > <1975000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + swbst_reg: swbst { > > + regulator-min-microvolt = > > <5000000>; > > + regulator-max-microvolt = > > <5150000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + snvs_reg: vsnvs { > > + regulator-min-microvolt = > > <1000000>; > > + regulator-max-microvolt = > > <3000000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + vref_reg: vrefddr { > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + vgen1_reg: vgen1 { > > + regulator-min-microvolt = > > <800000>; > > + regulator-max-microvolt = > > <1550000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + vgen2_reg: vgen2 { > > + regulator-min-microvolt = > > <800000>; > > + regulator-max-microvolt = > > <1550000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + vgen3_reg: vgen3 { > > + regulator-min-microvolt = > > <1800000>; > > + regulator-max-microvolt = > > <3300000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + vgen4_reg: vgen4 { > > + regulator-min-microvolt = > > <1800000>; > > + regulator-max-microvolt = > > <3300000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + vgen5_reg: vgen5 { > > + regulator-min-microvolt = > > <1800000>; > > + regulator-max-microvolt = > > <3300000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + vgen6_reg: vgen6 { > > + regulator-min-microvolt = > > <1800000>; > > + regulator-max-microvolt = > > <3300000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + }; > > + }; > > + > > + codec: sgtl5000 at 0a { > > + compatible = "fsl,sgtl5000"; > > + reg = <0x0a>; > > + clocks = <&clks 201>; > > + VDDA-supply = <®_2p5v>; > > + VDDIO-supply = <®_3p3v>; > > Nit: The device tree bindings mention two more properties as required > properties: > micbias-resistor-k-ohms > micbias-voltage-m-volts > > However, both have "If this node is not mentioned", hence I guess > they > are actually optional, but maybe we want to set an explicit value > here? Remember we don't make use of any of that microphone bias stuff on any of our Apalis hardware. > > + }; > > + > > + /* STMPE811 touch screen controller */ > > + stmpe811 at 41 { > > + compatible = "st,stmpe811"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_touch_int>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x41>; > > + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; > > + interrupt-parent = <&gpio4>; > > + interrupt-controller; > > + id = <0>; > > + blocks = <0x5>; > > + irq-trigger = <0x1>; > > + stmpe_touchscreen { > > + compatible = "st,stmpe-ts"; > > + reg = <0>; > > + /* 3.25 MHz ADC clock speed */ > > + st,adc-freq = <1>; > > + /* 8 sample average control */ > > + st,ave-ctrl = <3>; > > + /* 7 length fractional part in z */ > > + st,fraction-z = <7>; > > + /* > > + ?* 50 mA typical 80 mA max touchscreen > > drivers > > + ?* current limit value > > + ?*/ > > + st,i-drive = <1>; > > + /* 12-bit ADC */ > > + st,mod-12b = <1>; > > + /* internal ADC reference */ > > + st,ref-sel = <0>; > > + /* ADC converstion time: 80 clocks */ > > + st,sample-time = <4>; > > + /* 1 ms panel driver settling time */ > > + st,settling = <3>; > > + /* 5 ms touch detect interrupt delay */ > > + st,touch-det-delay = <5>; > > + }; > > + }; > > +}; > > + > > +/* > > + * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 201/203 (unused) > > + */ > > +&i2c3 { > > + clock-frequency = <100000>; > > + pinctrl-names = "default", "recovery"; > > + pinctrl-0 = <&pinctrl_i2c3>; > > + pinctrl-1 = <&pinctrl_i2c3_recovery>; > > + scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; > > + sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; > > + status = "disabled"; > > +}; > > + > > +/* PAD Ctrl values for common settings */ > > +/* > > + * (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | PAD_CTL_PKE > > | > > + *??PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) > > + */ > > +#define PAD_CTRL_HYS_PU 0x1b0b0 > > + > > +/* > > + * (PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | > > + *??PAD_CTL_DSE_40ohm) > > + */ > > +#define PAD_CTRL_HYS_PD 0x130b0 > > + > > +/* > > + * (PAD_CTL_PUS_22K_UP | PAD_CTL_PUE | PAD_CTL_PKE | > > PAD_CTL_SPEED_LOW | > > + *??PAD_CTL_DSE_80ohm) > > + */ > > +#define PAD_CTRL_PU_22k 0x0f058 > > + > > +&iomuxc { > > I think it is a convention to move iomuxc at the very end for better > readability of the rest. At least the Vybrid dts and the more > recently > added imx7d-sdb.dts follow this rule. Yes, while the Tegras have it at the beginning NXP wants it at the end (;-p). > > + ecspi { > > + pinctrl_ecspi1: ecspi1grp { > > + fsl,pins = < > > + MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO > > 0x100b1 > > + MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI > > 0x100b1 > > + MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK > > 0x100b1 > > + >; > > + }; > > + pinctrl_ecspi2: ecspi2grp { > > + fsl,pins = < > > + MX6QDL_PAD_EIM_OE__ECSPI2_MISO > > 0x100b1 > > + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI > > 0x100b1 > > + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK > > 0x100b1 > > + >; > > + }; > > + pinctrl_spi_cs1: spi_cs1 { > > + fsl,pins = < > > + /* SPI1 cs */ > > + MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 > > 0x000b1 > > + >; > > + }; > > + pinctrl_spi_cs2: spi_cs2 { > > + fsl,pins = < > > + /* SPI2 cs */ > > + MX6QDL_PAD_EIM_RW__GPIO2_IO26 > > 0x000b1 > > + >; > > + }; > > + }; > > + > > + flexcan { > > + pinctrl_flexcan1: flexcan1grp { > > + fsl,pins = < > > + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX > > 0x1b0b0 > > + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX > > 0x1b0b0 > > + >; > > + }; > > + pinctrl_flexcan2: flexcan2grp { > > + fsl,pins = < > > + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX > > 0x1b0b0 > > + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX > > 0x1b0b0 > > + >; > > + }; > > + }; > > + > > + gpio { > > + pinctrl_apalis_gpio1: apalis_gpio1 { > > + fsl,pins = < > > + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 > > PAD_CTRL_HYS_PD > > + >; > > + }; > > + pinctrl_apalis_gpio2: apalis_gpio2 { > > + fsl,pins = < > > + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 > > PAD_CTRL_HYS_PD > > + >; > > + }; > > + pinctrl_apalis_gpio3: apalis_gpio3 { > > + fsl,pins = < > > + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 > > PAD_CTRL_HYS_PD > > + >; > > + }; > > + pinctrl_apalis_gpio4: apalis_gpio4 { > > + fsl,pins = < > > + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 > > PAD_CTRL_HYS_PD > > + >; > > + }; > > + pinctrl_apalis_gpio5: apalis_gpio5 { > > + fsl,pins = < > > + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 > > PAD_CTRL_HYS_PD > > + >; > > + }; > > + pinctrl_apalis_gpio6: apalis_gpio6 { > > + fsl,pins = < > > + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 > > + PAD_CTRL_HYS_PD > > The 80 character limit normally is not enforced for device trees, > hence > I would remove that line break here... Yes, and then trying to teach patman to actually ignore that warning (;-p). > > + >; > > + }; > > + pinctrl_apalis_gpio7: apalis_gpio7 { > > + fsl,pins = < > > + MX6QDL_PAD_GPIO_2__GPIO1_IO02 > > PAD_CTRL_HYS_PD > > + >; > > + }; > > + pinctrl_apalis_gpio8: apalis_gpio8 { > > + fsl,pins = < > > + MX6QDL_PAD_GPIO_6__GPIO1_IO06 > > PAD_CTRL_HYS_PD > > + >; > > + }; > > + pinctrl_gpio_keys: gpio_keys { > > + fsl,pins = < > > + /* Power Button */ > > + MX6QDL_PAD_GPIO_4__GPIO1_IO04 > > PAD_CTRL_HYS_PU > > + >; > > + }; > > + }; > > + > > + hdmi { > > + pinctrl_hdmi_cec: hdmicecgrp { > > + fsl,pins = < > > + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_L > > INE 0x1f8b0 > > + >; > > + }; > > + }; > > + > > + i2c { > > + pinctrl_i2c_ddc: i2c_ddc { > > + fsl,pins = < > > + /* DDC bitbang */ > > + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 > > PAD_CTRL_HYS_PU > > + MX6QDL_PAD_EIM_D16__GPIO3_IO16 > > PAD_CTRL_HYS_PU > > + >; > > + }; > > + pinctrl_i2c1: i2c1grp { > > + fsl,pins = < > > + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA > > 0x4001b8b1 > > + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL > > 0x4001b8b1 > > + >; > > + }; > > + pinctrl_i2c3: i2c3grp { > > + fsl,pins = < > > + MX6QDL_PAD_EIM_D17__I2C3_SCL > > 0x4001b8b1 > > + MX6QDL_PAD_EIM_D18__I2C3_SDA > > 0x4001b8b1 > > + >; > > + }; > > + pinctrl_i2c3_recovery: i2c3-recoverygrp { > > + fsl,pins = < > > + MX6QDL_PAD_EIM_D17__GPIO3_IO17 > > 0x4001b8b1 > > + MX6QDL_PAD_EIM_D18__GPIO3_IO18 > > 0x4001b8b1 > > + >; > > + }; > > + }; > > + > > + /* pins used on module */ > > + imx6q-apalis { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_reset_moci > > &pinctrl_emmc_reset>; > > + pinctrl_audmux: audmuxgrp { > > + fsl,pins = < > > + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC > > 0x130b0 > > + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD > > 0x130b0 > > + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS > > 0x130b0 > > + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD > > 0x130b0 > > + >; > > + }; > > + pinctrl_audmux_mclk: audmux_mclk { > > + fsl,pins = < > > + /* SGTL5000 sys_mclk */ > > + MX6QDL_PAD_GPIO_5__CCM_CLKO1 > > 0x130b0 > > + >; > > + }; > > + pinctrl_emmc_reset: emmc_reset { > > + fsl,pins = < > > + /* eMMC reset, leave it alone */ > > + MX6QDL_PAD_SD3_RST__GPIO7_IO08 > > PAD_CTRL_PU_22k > > + >; > > + }; > > + pinctrl_enet: enetgrp { > > + fsl,pins = < > > + MX6QDL_PAD_ENET_MDIO__ENET_MDIO > > 0x100b0 > > + MX6QDL_PAD_ENET_MDC__ENET_MDC > > 0x100b0 > > + MX6QDL_PAD_RGMII_TXC__RGMII_TXC > > 0x100b0 > > + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 > > 0x100b0 > > + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 > > 0x100b0 > > + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 > > 0x100b0 > > + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 > > 0x100b0 > > + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_ > > CTL 0x100b0 > > + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_C > > LK 0x100b0 > > + MX6QDL_PAD_RGMII_RXC__RGMII_RXC > > 0x1b0b0 > > + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 > > 0x1b0b0 > > + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 > > 0x1b0b0 > > + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 > > 0x1b0b0 > > + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 > > 0x1b0b0 > > + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_ > > CTL 0x1b0b0 > > + >; > > + }; > > + pinctrl_enet_ctrl: enet_ctrlgrp { > > + fsl,pins = < > > + /* Ethernet PHY reset */ > > + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 > > 0x000b0 > > + /* Ethernet PHY interrupt */ > > + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 > > 0x000b1 > > + >; > > + }; > > + pinctrl_i2c2: i2c2grp { > > + fsl,pins = < > > + MX6QDL_PAD_KEY_COL3__I2C2_SCL > > 0x4001b8b1 > > + MX6QDL_PAD_KEY_ROW3__I2C2_SDA > > 0x4001b8b1 > > + >; > > + }; > > + pinctrl_ipu2_vdac: ipu2vdacgrp { > > + fsl,pins = < > > + MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_ > > DISP_CLK 0xd1 > > + MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN > > 15???????0xd1 > > + MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN0 > > 2????????0xd1 > > + MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN0 > > 3????????0xd1 > > + MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_ > > DATA00???0xf9 > > + MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_ > > DATA01???0xf9 > > + MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_ > > DATA02???0xf9 > > + MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_ > > DATA03???0xf9 > > + MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_ > > DATA04???0xf9 > > + MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_ > > DATA05???0xf9 > > + MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_ > > DATA06???0xf9 > > + MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_ > > DATA07???0xf9 > > + MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_ > > DATA08???0xf9 > > + MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_ > > DATA09???0xf9 > > + MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0 > > _DATA10??0xf9 > > + MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0 > > _DATA11??0xf9 > > + MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0 > > _DATA12??0xf9 > > + MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0 > > _DATA13??0xf9 > > + MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0 > > _DATA14??0xf9 > > + MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0 > > _DATA15??0xf9 > > + >; > > + }; > > + pinctrl_regulator_usbhub_pwr: > > gpio_regulator_usbhub_pwr { > > + fsl,pins = < > > + /* USBH_HUB_EN */ > > + MX6QDL_PAD_EIM_D28__GPIO3_IO28 > > PAD_CTRL_PU_22k > > + >; > > + }; > > + pinctrl_reset_moci: gpio_reset_moci { > > + fsl,pins = < > > + /* RESET_MOCI control */ > > + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 > > + PAD_CTRL_PU_22k > > + >; > > + }; > > + pinctrl_touch_int: touch_intgrp { > > + fsl,pins = < > > + /* STMPE811 interrupt */ > > + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 > > PAD_CTRL_HYS_PU > > + >; > > + }; > > + pinctrl_usdhc3: usdhc3grp { > > + fsl,pins = < > > + MX6QDL_PAD_SD3_CMD__SD3_CMD????0x1 > > 7059 > > + MX6QDL_PAD_SD3_CLK__SD3_CLK????0x1 > > 0059 > > + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 > > 0x17059 > > + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 > > 0x17059 > > + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 > > 0x17059 > > + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 > > 0x17059 > > + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 > > 0x17059 > > + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 > > 0x17059 > > + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 > > 0x17059 > > + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 > > 0x17059 > > + >; > > + }; > > + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { /* > > 100Mhz */ > > I do not have a strong opinion on comments, but if they are pure > duplication of what is already there, I kind of prefer to not add > them... Agreed. > > + fsl,pins = < > > + MX6QDL_PAD_SD3_CMD__SD3_CMD > > 0x170B9 > > + MX6QDL_PAD_SD3_CLK__SD3_CLK > > 0x100B9 > > + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 > > 0x170B9 > > + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 > > 0x170B9 > > + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 > > 0x170B9 > > + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 > > 0x170B9 > > + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 > > 0x170B9 > > + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 > > 0x170B9 > > + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 > > 0x170B9 > > + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 > > 0x170B9 > > + >; > > + }; > > + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { /* > > 200Mhz */ > > + fsl,pins = < > > + MX6QDL_PAD_SD3_CMD__SD3_CMD > > 0x170F9 > > + MX6QDL_PAD_SD3_CLK__SD3_CLK > > 0x100F9 > > + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 > > 0x170F9 > > + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 > > 0x170F9 > > + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 > > 0x170F9 > > + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 > > 0x170F9 > > + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 > > 0x170F9 > > + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 > > 0x170F9 > > + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 > > 0x170F9 > > + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 > > 0x170F9 > > + >; > > + }; > > + }; > > + > > + ipu1 { > > + pinctrl_ipu1_lcdif: ipu1lcdifgrp { > > + fsl,pins = < > > + MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_ > > CLK 0x61 > > + /* DE */ > > + MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN1 > > 5 0x61 > > + /* HSync */ > > + MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN0 > > 2 0x61 > > + /* VSync */ > > + MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN0 > > 3 0x61 > > + MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DAT > > A00 0x61 > > + MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DAT > > A01 0x61 > > + MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DAT > > A02 0x61 > > + MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DAT > > A03 0x61 > > + MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DAT > > A04 0x61 > > + MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DAT > > A05 0x61 > > + MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DAT > > A06 0x61 > > + MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DAT > > A07 0x61 > > + MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DAT > > A08 0x61 > > + MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DAT > > A09 0x61 > > + MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DAT > > A10 0x61 > > + MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DAT > > A11 0x61 > > + MX6QDL_PAD_EIM_A17__IPU1_DISP1_DAT > > A12 0x61 > > + MX6QDL_PAD_EIM_A18__IPU1_DISP1_DAT > > A13 0x61 > > + MX6QDL_PAD_EIM_A19__IPU1_DISP1_DAT > > A14 0x61 > > + MX6QDL_PAD_EIM_A20__IPU1_DISP1_DAT > > A15 0x61 > > + MX6QDL_PAD_EIM_A21__IPU1_DISP1_DAT > > A16 0x61 > > + MX6QDL_PAD_EIM_A22__IPU1_DISP1_DAT > > A17 0x61 > > + MX6QDL_PAD_EIM_A23__IPU1_DISP1_DAT > > A18 0x61 > > + MX6QDL_PAD_EIM_A24__IPU1_DISP1_DAT > > A19 0x61 > > + MX6QDL_PAD_EIM_D31__IPU1_DISP1_DAT > > A20 0x61 > > + MX6QDL_PAD_EIM_D30__IPU1_DISP1_DAT > > A21 0x61 > > + MX6QDL_PAD_EIM_D26__IPU1_DISP1_DAT > > A22 0x61 > > + MX6QDL_PAD_EIM_D27__IPU1_DISP1_DAT > > A23 0x61 > > + >; > > + }; > > + pinctrl_cam_mclk: cam_mclk { > > + fsl,pins = < > > + /* CAM sys_mclk */ > > + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 > > 0x00b0 > > + >; > > + }; > > + pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel > > camera */ > > + fsl,pins = < > > + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_D > > ATA12??0xb0b1 > > + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_D > > ATA13??0xb0b1 > > + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_D > > ATA14??0xb0b1 > > + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_D > > ATA15??0xb0b1 > > + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_D > > ATA16??0xb0b1 > > + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_D > > ATA17??0xb0b1 > > + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_D > > ATA18??0xb0b1 > > + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_D > > ATA19??0xb0b1 > > + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_ > > PIXCLK 0xb0b1 > > + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HS > > YNC????0xb0b1 > > + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_V > > SYNC???0xb0b1 > > + >; > > + }; > > + }; > > + > > + pwm { > > + pinctrl_pwm1: pwm1grp { > > + fsl,pins = < > > + MX6QDL_PAD_GPIO_9__PWM1_OUT > > 0x1b0b1 > > + >; > > + }; > > + pinctrl_pwm2: pwm2grp { > > + fsl,pins = < > > + MX6QDL_PAD_GPIO_1__PWM2_OUT > > 0x1b0b1 > > + >; > > + }; > > + pinctrl_pwm3: pwm3grp { > > + fsl,pins = < > > + MX6QDL_PAD_SD4_DAT1__PWM3_OUT > > 0x1b0b1 > > + >; > > + }; > > + pinctrl_pwm4: pwm4grp { > > + fsl,pins = < > > + MX6QDL_PAD_SD4_DAT2__PWM4_OUT > > 0x1b0b1 > > + >; > > + }; > > + }; > > + > > + spdif { > > + pinctrl_spdif: spdifgrp { > > + fsl,pins = < > > + MX6QDL_PAD_GPIO_16__SPDIF_IN??0x1b > > 0b0 > > + MX6QDL_PAD_GPIO_17__SPDIF_OUT > > 0x1b0b0 > > + >; > > + }; > > + }; > > + > > + uart1 { > > + pinctrl_uart1_dce: uart1-dcegrp { > > + fsl,pins = < > > + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DA > > TA 0x1b0b1 > > + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DA > > TA 0x1b0b1 > > + >; > > + }; > > + > > + /* DTE mode */ > > + pinctrl_uart1_dte: uart1-dtegrp { > > + fsl,pins = < > > + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DA > > TA 0x1b0b1 > > + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DA > > TA 0x1b0b1 > > + MX6QDL_PAD_EIM_D19__UART1_RTS_B > > 0x1b0b1 > > + MX6QDL_PAD_EIM_D20__UART1_CTS_B > > 0x1b0b1 > > + >; > > + }; > > + > > + /* Additional DTR, DSR, DCD */ > > + pinctrl_uart1_ctrl: uart1-ctrlgrp { > > + fsl,pins = < > > + MX6QDL_PAD_EIM_D23__UART1_DCD_B > > 0x1b0b0 > > + MX6QDL_PAD_EIM_D24__UART1_DTR_B > > 0x1b0b0 > > + MX6QDL_PAD_EIM_D25__UART1_DSR_B > > 0x1b0b0 > > + >; > > + }; > > + }; > > + > > + uart2 { > > + pinctrl_uart2_dce: uart2-dcegrp { > > + fsl,pins = < > > + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA > > 0x1b0b1 > > + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA > > 0x1b0b1 > > + >; > > + }; > > + > > + /* DTE mode */ > > + pinctrl_uart2_dte: uart2grp-dte { > > + fsl,pins = < > > + MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA > > 0x1b0b1 > > + MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA > > 0x1b0b1 > > + MX6QDL_PAD_SD4_DAT6__UART2_RTS_B > > 0x1b0b1 > > + MX6QDL_PAD_SD4_DAT5__UART2_CTS_B > > 0x1b0b1 > > + >; > > + }; > > + }; > > + > > + uart4 { > > + pinctrl_uart4_dce: uart4-dcegrp { > > + fsl,pins = < > > + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA > > 0x1b0b1 > > + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA > > 0x1b0b1 > > + >; > > + }; > > + > > + /* DTE mode */ > > + pinctrl_uart4_dte: uart4-dtegrp { > > + fsl,pins = < > > + MX6QDL_PAD_KEY_COL0__UART4_RX_DATA > > 0x1b0b1 > > + MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA > > 0x1b0b1 > > + >; > > + }; > > + }; > > + > > + uart5 { > > + pinctrl_uart5_dce: uart5-dcegrp { > > + fsl,pins = < > > + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA > > 0x1b0b1 > > + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA > > 0x1b0b1 > > + >; > > + }; > > + > > + /* DTE mode */ > > + pinctrl_uart5_dte: uart5-dtegrp { > > + fsl,pins = < > > + MX6QDL_PAD_KEY_COL1__UART5_RX_DATA > > 0x1b0b1 > > + MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA > > 0x1b0b1 > > + >; > > + }; > > + }; > > + > > + usbh { > > + pinctrl_regulator_usbh_pwr: > > gpio_regulator_usbh_pwr { > > + fsl,pins = < > > + /* USBH_EN */ > > + MX6QDL_PAD_GPIO_0__GPIO1_IO00 > > PAD_CTRL_PU_22k > > + >; > > + }; > > + }; > > + > > + usbotg { > > + pinctrl_usbotg: usbotggrp { > > + fsl,pins = < > > + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID > > 0x17059 > > + >; > > + }; > > + pinctrl_regulator_usbotg_pwr: > > gpio_regulator_usbotg_pwr { > > + fsl,pins = < > > + /* USBO power en */ > > + MX6QDL_PAD_EIM_D22__GPIO3_IO22 > > PAD_CTRL_PU_22k > > + >; > > + }; > > + }; > > + > > + usdhc { > > + pinctrl_mmc_cd: gpio_mmc_cd { > > + fsl,pins = < > > + ?/* MMC1 CD */ > > + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 > > 0x000b0 > > + >; > > + }; > > + pinctrl_sd_cd: gpio_sd_cd { > > + fsl,pins = < > > + /* SD1 CD */ > > + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 > > 0x000b0 > > + >; > > + }; > > + pinctrl_usdhc1: usdhc1grp { > > + fsl,pins = < > > + MX6QDL_PAD_SD1_CMD__SD1_CMD????0x1 > > 7071 > > + MX6QDL_PAD_SD1_CLK__SD1_CLK????0x1 > > 0071 > > + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 > > 0x17071 > > + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 > > 0x17071 > > + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 > > 0x17071 > > + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 > > 0x17071 > > + MX6QDL_PAD_NANDF_D0__SD1_DATA4 > > 0x17071 > > + MX6QDL_PAD_NANDF_D1__SD1_DATA5 > > 0x17071 > > + MX6QDL_PAD_NANDF_D2__SD1_DATA6 > > 0x17071 > > + MX6QDL_PAD_NANDF_D3__SD1_DATA7 > > 0x17071 > > + >; > > + }; > > + pinctrl_usdhc2: usdhc2grp { > > + fsl,pins = < > > + MX6QDL_PAD_SD2_CMD__SD2_CMD????0x1 > > 7071 > > + MX6QDL_PAD_SD2_CLK__SD2_CLK????0x1 > > 0071 > > + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 > > 0x17071 > > + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 > > 0x17071 > > + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 > > 0x17071 > > + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 > > 0x17071 > > + >; > > + }; > > + }; > > +}; > > + > > +&ldb { > > + status = "okay"; > > +}; > > + > > +&pwm1 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_pwm1>; > > + status = "disabled"; > > +}; > > + > > +&pwm2 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_pwm2>; > > + status = "disabled"; > > +}; > > + > > +&pwm3 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_pwm3>; > > + status = "disabled"; > > +}; > > + > > +&pwm4 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_pwm4>; > > + status = "disabled"; > > +}; > > + > > +&spdif { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_spdif>; > > + status = "disabled"; > > +}; > > + > > +&ssi1 { > > + fsl,mode = "i2s-slave"; > > + status = "okay"; > > +}; > > + > > +&uart1 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; > > + fsl,dte-mode; > > + fsl,uart-has-rtscts; > > + status = "disabled"; > > +}; > > + > > +&uart2 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_uart2_dte>; > > + fsl,dte-mode; > > + fsl,uart-has-rtscts; > > + status = "disabled"; > > +}; > > + > > +&uart4 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_uart4_dte>; > > + fsl,dte-mode; > > + status = "disabled"; > > +}; > > + > > +&uart5 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_uart5_dte>; > > + fsl,dte-mode; > > + status = "disabled"; > > +}; > > + > > +&usbh1 { > > + vbus-supply = <®_usb_host_vbus>; > > + status = "disabled"; > > +}; > > + > > +&usbotg { > > + vbus-supply = <®_usb_otg_vbus>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_usbotg>; > > + disable-over-current; > > + status = "disabled"; > > +}; > > + > > +/* MMC1 */ > > +&usdhc1 { > > + label = "MMC1"; > > This... > > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; > > + cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; > > + vmmc-supply = <®_3p3v>; > > + bus-width = <8>; > > + voltage-ranges = <3300 3300>; > > + status = "disabled"; > > +}; > > + > > +/* SD1 */ > > +&usdhc2 { > > + label = "SD1"; > > ...and this seem not to be specified upstream? (at least not in > Documentation/devicetree/bindings/mmc/mmc.txt?) > Not sure about this... Or is label a common convention and hence > available for all nodes? Yes, I guess one can put labels anywhere but I also don't see what the exact purpose of them should be in this case so I will drop them. > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; > > + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; > > + vmmc-supply = <®_3p3v>; > > + bus-width = <4>; > > + voltage-ranges = <3300 3300>; > > + status = "disabled"; > > +}; > > + > > +/* eMMC */ > > +&usdhc3 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_usdhc3>; > > + vmmc-supply = <®_3p3v>; > > + bus-width = <8>; > > + voltage-ranges = <3300 3300>; > > + non-removable; > > + status = "okay"; > > +}; > > + > > +&weim { > > + status = "disabled"; /* weim signals not accessible on > > i.MX6 */ > > They are accessible on the i.MX6 SoC.. but maybe "on Apalis iMX6Q/D". > Or > just remove the comment, since that is kind of what disabled says? Yes, that comment seems bogus and will be dropped. > > +}; > > Otherwise: > Reviewed-by: Stefan Agner Thanks! > -- > Stefan Cheers Marcel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marcel Ziswiler Subject: Re: [PATCH v2 1/2] ARM: dts: imx6: Add support for Toradex Apalis iMX6Q/D SoM Date: Fri, 8 Jan 2016 08:28:58 +0000 Message-ID: <1452241735.3357.11.camel@toradex.com> References: <1452011942-11940-1-git-send-email-marcel.ziswiler@toradex.com> <1452011942-11940-2-git-send-email-marcel.ziswiler@toradex.com> <7e21f1c5e2e30fb2c7bfd9d47ba6e9d9@agner.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <7e21f1c5e2e30fb2c7bfd9d47ba6e9d9@agner.ch> Content-Language: en-US Content-ID: <285581404C98994FBABA1C8D045EA4DB@eurprd05.prod.outlook.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: "stefan@agner.ch" Cc: "mark.rutland@arm.com" , "devicetree@vger.kernel.org" , "stillcompiling@gmail.com" , "linux@arm.linux.org.uk" , "pawel.moll@arm.com" , "ijc+devicetree@hellion.org.uk" , "shawnguo@kernel.org" , "linux-kernel@vger.kernel.org" , "robh+dt@kernel.org" , "kernel@pengutronix.de" , "galak@codeaurora.org" , "ynezz@true.cz" , "shawn.guo@linaro.org" , "festevam@gmail.com" , "linux-arm-kernel@lists.infradead.org" , "l.stach@pengutronix.de" List-Id: devicetree@vger.kernel.org SGkgU3RlZmFuDQoNCk9uIFdlZCwgMjAxNi0wMS0wNiBhdCAyMjoyOSAtMDgwMCwgU3RlZmFuIEFn bmVyIHdyb3RlOg0KPiBIaSBNYXJjZWwsDQo+IA0KPiBPbiAyMDE2LTAxLTA1IDA4OjM5LCBNYXJj ZWwgWmlzd2lsZXIgd3JvdGU6DQo+ID4gRnJvbTogUGV0ciDFoHRldGlhciA8eW5lenpAdHJ1ZS5j ej4NCj4gPiANCj4gPiBTaWduZWQtb2ZmLWJ5OiBQZXRyIMWgdGV0aWFyIDx5bmV6ekB0cnVlLmN6 Pg0KPiA+IFNpZ25lZC1vZmYtYnk6IE1hcmNlbCBaaXN3aWxlciA8bWFyY2VsLnppc3dpbGVyQHRv cmFkZXguY29tPg0KPiA+IC0tLQ0KPiA+IA0KPiA+IENoYW5nZXMgaW4gdjI6DQo+ID4gLSBjbGFy aWZ5IGV4YWN0IEFwYWxpcyBpTVg2US9EIFNvTSB0eXBlIGluIGNvdmVyIGxldHRlcg0KPiA+IC0g Y2xhcmlmeSBleGFjdCBBcGFsaXMgaU1YNlEvRCBtb2R1bGUgdHlwZSBhbmQgSXhvcmEgY2Fycmll ciBib2FyZA0KPiA+IGluIG1vZGVsDQo+ID4gwqAgbm9kZQ0KPiA+IC0gZ290IHJpZCBvZiBvYnNv bGV0ZSBtbWMgYWxpYXNlcw0KPiA+IC0gd29ya2luZyBTR1RMNTAwMCBhdWRpby9zb3VuZCBpbnRl Z3JhdGlvbg0KPiA+IC0gd29ya2luZyBTVE1QRTgxMSB0b3VjaCBzY3JlZW4gY29udHJvbGxlciBp bnRlZ3JhdGlvbg0KPiA+IC0gaW50ZWdyYXRlZCByZXZpZXcgZmVlZGJhY2sgZnJvbSBMdWNhcw0K PiA+IC0gbGVmdCBhbmQgZXZlbiBhZGRlZCBzb21lIG1vcmUgY29tbWVudHMgYXMgSSBkb24ndCBz ZWUgd2h5IHB1dHRpbmcNCj4gPiBhbnkNCj4gPiDCoCBleHBsYW5hdG9yeSBjb21tZW50cyBpbiBk dHMnIHNob3VsZCBiZSBzdWNoIGEgYmFkIHRoaW5nIHRvIGRvDQo+ID4gLSBjb21wbGV0ZWx5IGdv dCByaWQgb2YgdGhlIG1lbW9yeSBub2RlIGFzIHRoYXQgaXMgc29tZXRoaW5nDQo+ID4gdHlwaWNh bGx5IGZpbGxlZA0KPiA+IMKgIGluIGJ5IHRoZSBib290IGxvYWRlciBlLmcuIFUtQm9vdA0KPiA+ IC0gd2l0aG91dCB0aGUgcmVndWxhdG9ycyBzaW1wbGUtYnVzIGl0IG5vIGxvbmdlciBib290cw0K PiA+IC0gZXZlbiB0aG91Z2ggd2Ugc3VwcG9zZWRseSBzaGlwcGVkIGEgZmV3IGh1bmRyZWQgVjEu MGEgbW9kdWxlcw0KPiA+IGRyb3AgRENFIFVBUlQNCj4gPiDCoCBzdXBwb3J0IGZvciBub3cgYW5k IHNpbXBsaWZ5IGZpbGUgbGF5b3V0DQo+ID4gLSByZXBsYWNlZCBvYnNvbGV0ZSBuby0xLTgtdiBi eSBtYWlubGluZSBzdXBwb3J0ZWQgdm9sdGFnZS1yYW5nZXMgPQ0KPiA+IDwzMzAwIDMzMDA+DQo+ ID4gwqAgdXNkaGMgcHJvcGVydHkgYW5kIHllcyBjYXJkIGRldGVjdHMgYXJlIGluZGVlZCBhY3Rp dmUgbG93ICg7LXApDQo+ID4gLSBpbnRlZ3JhdGVkIHJldmlldyBmZWVkYmFjayBmcm9tIFN0ZWZh bg0KPiA+IC0gZml4ZWQgRXRoZXJuZXQgUEhZIHJlc2V0ICYgaW50ZXJydXB0IChyZXF1aXJlcyBN aWNyZWwgUEhZIGRyaXZlcg0KPiA+IHRvIGJlDQo+ID4gwqAgZW5hYmxlZCkNCj4gPiAtIGZpeGVk IEhETUkgRERDIChyZXF1aXJlcyBHUElPLWJhc2VkIGJpdGJhbmdpbmcgSTJDIHRvIGJlIGVuYWJs ZWQpDQo+ID4gLSBmaXhlZCBTUERJRg0KPiA+IA0KPiA+IMKgYXJjaC9hcm0vYm9vdC9kdHMvaW14 NnFkbC1hcGFsaXMuZHRzaSB8IDEwNDANCj4gPiArKysrKysrKysrKysrKysrKysrKysrKysrKysr KysrKysNCj4gPiDCoDEgZmlsZSBjaGFuZ2VkLCAxMDQwIGluc2VydGlvbnMoKykNCj4gPiDCoGNy ZWF0ZSBtb2RlIDEwMDY0NCBhcmNoL2FybS9ib290L2R0cy9pbXg2cWRsLWFwYWxpcy5kdHNpDQo+ ID4gDQo+ID4gZGlmZiAtLWdpdCBhL2FyY2gvYXJtL2Jvb3QvZHRzL2lteDZxZGwtYXBhbGlzLmR0 c2kNCj4gPiBiL2FyY2gvYXJtL2Jvb3QvZHRzL2lteDZxZGwtYXBhbGlzLmR0c2kNCj4gPiBuZXcg ZmlsZSBtb2RlIDEwMDY0NA0KPiA+IGluZGV4IDAwMDAwMDAuLjYxMDRlMmUNCj4gPiAtLS0gL2Rl di9udWxsDQo+ID4gKysrIGIvYXJjaC9hcm0vYm9vdC9kdHMvaW14NnFkbC1hcGFsaXMuZHRzaQ0K PiA+IEBAIC0wLDAgKzEsMTA0MCBAQA0KPiA+ICsvKg0KPiA+ICsgKiBDb3B5cmlnaHQgMjAxNC0y MDE2IFRvcmFkZXggQUcNCj4gPiArICogQ29weXJpZ2h0IDIwMTIgRnJlZXNjYWxlIFNlbWljb25k dWN0b3IsIEluYy4NCj4gPiArICogQ29weXJpZ2h0IDIwMTEgTGluYXJvIEx0ZC4NCj4gPiArICoN Cj4gPiArICogVGhpcyBmaWxlIGlzIGR1YWwtbGljZW5zZWQ6IHlvdSBjYW4gdXNlIGl0IGVpdGhl ciB1bmRlciB0aGUNCj4gPiB0ZXJtcw0KPiA+ICsgKiBvZiB0aGUgR1BMIG9yIHRoZSBYMTEgbGlj ZW5zZSwgYXQgeW91ciBvcHRpb24uIE5vdGUgdGhhdCB0aGlzDQo+ID4gZHVhbA0KPiA+ICsgKiBs aWNlbnNpbmcgb25seSBhcHBsaWVzIHRvIHRoaXMgZmlsZSwgYW5kIG5vdCB0aGlzIHByb2plY3Qg YXMgYQ0KPiA+ICsgKiB3aG9sZS4NCj4gPiArICoNCj4gPiArICrCoMKgYSkgVGhpcyBmaWxlIGlz IGZyZWUgc29mdHdhcmU7IHlvdSBjYW4gcmVkaXN0cmlidXRlIGl0IGFuZC9vcg0KPiA+ICsgKsKg wqDCoMKgwqBtb2RpZnkgaXQgdW5kZXIgdGhlIHRlcm1zIG9mIHRoZSBHTlUgR2VuZXJhbCBQdWJs aWMgTGljZW5zZQ0KPiA+ICsgKsKgwqDCoMKgwqB2ZXJzaW9uIDIgYXMgcHVibGlzaGVkIGJ5IHRo ZSBGcmVlIFNvZnR3YXJlIEZvdW5kYXRpb24uDQo+ID4gKyAqDQo+ID4gKyAqwqDCoMKgwqDCoFRo aXMgZmlsZSBpcyBkaXN0cmlidXRlZCBpbiB0aGUgaG9wZSB0aGF0IGl0IHdpbGwgYmUgdXNlZnVs DQo+ID4gKyAqwqDCoMKgwqDCoGJ1dCBXSVRIT1VUIEFOWSBXQVJSQU5UWTsgd2l0aG91dCBldmVu IHRoZSBpbXBsaWVkIHdhcnJhbnR5DQo+ID4gb2YNCj4gPiArICrCoMKgwqDCoMKgTUVSQ0hBTlRB QklMSVRZIG9yIEZJVE5FU1MgRk9SIEEgUEFSVElDVUxBUiBQVVJQT1NFLsKgwqBTZWUNCj4gPiB0 aGUNCj4gPiArICrCoMKgwqDCoMKgR05VIEdlbmVyYWwgUHVibGljIExpY2Vuc2UgZm9yIG1vcmUg ZGV0YWlscy4NCj4gPiArICoNCj4gPiArICogT3IsIGFsdGVybmF0aXZlbHkNCj4gPiArICoNCj4g PiArICrCoMKgYikgUGVybWlzc2lvbiBpcyBoZXJlYnkgZ3JhbnRlZCwgZnJlZSBvZiBjaGFyZ2Us IHRvIGFueSBwZXJzb24NCj4gPiArICrCoMKgwqDCoMKgb2J0YWluaW5nIGEgY29weSBvZiB0aGlz IHNvZnR3YXJlIGFuZCBhc3NvY2lhdGVkDQo+ID4gZG9jdW1lbnRhdGlvbg0KPiA+ICsgKsKgwqDC oMKgwqBmaWxlcyAodGhlICJTb2Z0d2FyZSIpLCB0byBkZWFsIGluIHRoZSBTb2Z0d2FyZSB3aXRo b3V0DQo+ID4gKyAqwqDCoMKgwqDCoHJlc3RyaWN0aW9uLCBpbmNsdWRpbmcgd2l0aG91dCBsaW1p dGF0aW9uIHRoZSByaWdodHMgdG8gdXNlDQo+ID4gKyAqwqDCoMKgwqDCoGNvcHksIG1vZGlmeSwg bWVyZ2UsIHB1Ymxpc2gsIGRpc3RyaWJ1dGUsIHN1YmxpY2Vuc2UsDQo+ID4gYW5kL29yDQo+ID4g KyAqwqDCoMKgwqDCoHNlbGwgY29waWVzIG9mIHRoZSBTb2Z0d2FyZSwgYW5kIHRvIHBlcm1pdCBw ZXJzb25zIHRvIHdob20NCj4gPiB0aGUNCj4gPiArICrCoMKgwqDCoMKgU29mdHdhcmUgaXMgZnVy bmlzaGVkIHRvIGRvIHNvLCBzdWJqZWN0IHRvIHRoZSBmb2xsb3dpbmcNCj4gPiArICrCoMKgwqDC oMKgY29uZGl0aW9uczoNCj4gPiArICoNCj4gPiArICrCoMKgwqDCoMKgVGhlIGFib3ZlIGNvcHly aWdodCBub3RpY2UgYW5kIHRoaXMgcGVybWlzc2lvbiBub3RpY2Ugc2hhbGwNCj4gPiBiZQ0KPiA+ ICsgKsKgwqDCoMKgwqBpbmNsdWRlZCBpbiBhbGwgY29waWVzIG9yIHN1YnN0YW50aWFsIHBvcnRp b25zIG9mIHRoZQ0KPiA+IFNvZnR3YXJlLg0KPiA+ICsgKg0KPiA+ICsgKsKgwqDCoMKgwqBUSEUg U09GVFdBUkUgSVMgUFJPVklERUQgLCBXSVRIT1VUIFdBUlJBTlRZIE9GIEFOWSBLSU5EDQo+ID4g KyAqwqDCoMKgwqDCoEVYUFJFU1MgT1IgSU1QTElFRCwgSU5DTFVESU5HIEJVVCBOT1QgTElNSVRF RCBUTyBUSEUNCj4gPiBXQVJSQU5USUVTDQo+ID4gKyAqwqDCoMKgwqDCoE9GIE1FUkNIQU5UQUJJ TElUWSwgRklUTkVTUyBGT1IgQSBQQVJUSUNVTEFSIFBVUlBPU0UgQU5EDQo+ID4gKyAqwqDCoMKg wqDCoE5PTklORlJJTkdFTUVOVC4gSU4gTk8gRVZFTlQgU0hBTEwgVEhFIEFVVEhPUlMgT1IgQ09Q WVJJR0hUDQo+ID4gKyAqwqDCoMKgwqDCoEhPTERFUlMgQkUgTElBQkxFIEZPUiBBTlkgQ0xBSU0s IERBTUFHRVMgT1IgT1RIRVIgTElBQklMSVRZDQo+ID4gKyAqwqDCoMKgwqDCoFdIRVRIRVIgSU4g QU4gQUNUSU9OIE9GIENPTlRSQUNULCBUT1JUIE9SIE9USEVSV0lTRSwNCj4gPiBBUklTSU5HDQo+ ID4gKyAqwqDCoMKgwqDCoEZST00sIE9VVCBPRiBPUiBJTiBDT05ORUNUSU9OIFdJVEggVEhFIFNP RlRXQVJFIE9SIFRIRSBVU0UNCj4gPiBPUg0KPiA+ICsgKsKgwqDCoMKgwqBPVEhFUiBERUFMSU5H UyBJTiBUSEUgU09GVFdBUkUuDQo+ID4gKyAqLw0KPiA+ICsNCj4gPiArI2luY2x1ZGUgPGR0LWJp bmRpbmdzL2dwaW8vZ3Bpby5oPg0KPiA+ICsNCj4gPiArLyB7DQo+ID4gKwltb2RlbCA9ICJUb3Jh ZGV4IEFwYWxpcyBpTVg2US9EIE1vZHVsZSI7DQo+ID4gKwljb21wYXRpYmxlID0gInRvcmFkZXgs YXBhbGlzX2lteDZxIiwgImZzbCxpbXg2cSI7DQo+ID4gKw0KPiA+ICsJYmFja2xpZ2h0OiBiYWNr bGlnaHQgew0KPiA+ICsJCWNvbXBhdGlibGUgPSAicHdtLWJhY2tsaWdodCI7DQo+ID4gKwkJcHdt cyA9IDwmcHdtNCAwIDUwMDAwMDA+Ow0KPiA+ICsJCXN0YXR1cyA9ICJkaXNhYmxlZCI7DQo+ID4g Kwl9Ow0KPiA+ICsNCj4gPiArCS8qIEREQ19JMkM6IEkyQzJfU0RBL1NDTCBvbiBNWE0zIDIwNS8y MDcgKi8NCj4gPiArCWkyY2RkYzogaTJjQDAgew0KPiA+ICsJCWNvbXBhdGlibGUgPSAiaTJjLWdw aW8iOw0KPiA+ICsJCXBpbmN0cmwtbmFtZXMgPSAiZGVmYXVsdCI7DQo+ID4gKwkJcGluY3RybC0w ID0gPCZwaW5jdHJsX2kyY19kZGM+Ow0KPiA+ICsJCWdwaW9zID0gPCZncGlvMyAxNiBHUElPX0FD VElWRV9ISUdIIC8qIHNkYSAqLw0KPiA+ICsJCQnCoCZncGlvMiAzMCBHUElPX0FDVElWRV9ISUdI IC8qIHNjbCAqLw0KPiA+ICsJCQk+Ow0KPiA+ICsJCWkyYy1ncGlvLGRlbGF5LXVzID0gPDI+Owkv KiB+MTAwIGtIeiAqLw0KPiA+ICsJCXN0YXR1cyA9ICJva2F5IjsNCj4gPiArCX07DQo+ID4gKw0K PiA+ICsJcmVndWxhdG9ycyB7DQo+ID4gKwkJY29tcGF0aWJsZSA9ICJzaW1wbGUtYnVzIjsNCj4g PiArDQo+ID4gKwkJcmVnXzFwOHY6IDFwOHYgew0KPiA+ICsJCQljb21wYXRpYmxlID0gInJlZ3Vs YXRvci1maXhlZCI7DQo+ID4gKwkJCXJlZ3VsYXRvci1uYW1lID0gIjFQOFYiOw0KPiA+ICsJCQly ZWd1bGF0b3ItbWluLW1pY3Jvdm9sdCA9IDwxODAwMDAwPjsNCj4gPiArCQkJcmVndWxhdG9yLW1h eC1taWNyb3ZvbHQgPSA8MTgwMDAwMD47DQo+ID4gKwkJCXJlZ3VsYXRvci1hbHdheXMtb247DQo+ ID4gKwkJfTsNCj4gPiArDQo+ID4gKwkJcmVnXzJwNXY6IDJwNXYgew0KPiA+ICsJCQljb21wYXRp YmxlID0gInJlZ3VsYXRvci1maXhlZCI7DQo+ID4gKwkJCXJlZ3VsYXRvci1uYW1lID0gIjJQNVYi Ow0KPiA+ICsJCQlyZWd1bGF0b3ItbWluLW1pY3Jvdm9sdCA9IDwyNTAwMDAwPjsNCj4gPiArCQkJ cmVndWxhdG9yLW1heC1taWNyb3ZvbHQgPSA8MjUwMDAwMD47DQo+ID4gKwkJCXJlZ3VsYXRvci1h bHdheXMtb247DQo+ID4gKwkJfTsNCj4gPiArDQo+ID4gKwkJcmVnXzNwM3Y6IDNwM3Ygew0KPiA+ ICsJCQljb21wYXRpYmxlID0gInJlZ3VsYXRvci1maXhlZCI7DQo+ID4gKwkJCXJlZ3VsYXRvci1u YW1lID0gIjNQM1YiOw0KPiA+ICsJCQlyZWd1bGF0b3ItbWluLW1pY3Jvdm9sdCA9IDwzMzAwMDAw PjsNCj4gPiArCQkJcmVndWxhdG9yLW1heC1taWNyb3ZvbHQgPSA8MzMwMDAwMD47DQo+ID4gKwkJ CXJlZ3VsYXRvci1hbHdheXMtb247DQo+ID4gKwkJfTsNCj4gPiArDQo+ID4gKwkJcmVnX3VzYl9v dGdfdmJ1czogdXNiX290Z192YnVzIHsNCj4gPiArCQkJY29tcGF0aWJsZSA9ICJyZWd1bGF0b3It Zml4ZWQiOw0KPiA+ICsJCQlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOw0KPiA+ICsJCQlwaW5j dHJsLTAgPQ0KPiA+IDwmcGluY3RybF9yZWd1bGF0b3JfdXNib3RnX3B3cj47DQo+ID4gKwkJCXJl Z3VsYXRvci1uYW1lID0gInVzYl9vdGdfdmJ1cyI7DQo+ID4gKwkJCXJlZ3VsYXRvci1taW4tbWlj cm92b2x0ID0gPDUwMDAwMDA+Ow0KPiA+ICsJCQlyZWd1bGF0b3ItbWF4LW1pY3Jvdm9sdCA9IDw1 MDAwMDAwPjsNCj4gPiArCQkJZ3BpbyA9IDwmZ3BpbzMgMjIgR1BJT19BQ1RJVkVfSElHSD47DQo+ ID4gKwkJCWVuYWJsZS1hY3RpdmUtaGlnaDsNCj4gPiArCQkJc3RhdHVzID0gImRpc2FibGVkIjsN Cj4gPiArCQl9Ow0KPiA+ICsNCj4gPiArCQkvKiBvbiBtb2R1bGUgdXNiIGh1YiAqLw0KPiA+ICsJ CXJlZ191c2JfaG9zdF92YnVzX2h1YjogdXNiX2hvc3RfdmJ1c19odWIgew0KPiA+ICsJCQljb21w YXRpYmxlID0gInJlZ3VsYXRvci1maXhlZCI7DQo+ID4gKwkJCXBpbmN0cmwtbmFtZXMgPSAiZGVm YXVsdCI7DQo+ID4gKwkJCXBpbmN0cmwtMCA9DQo+ID4gPCZwaW5jdHJsX3JlZ3VsYXRvcl91c2Jo dWJfcHdyPjsNCj4gPiArCQkJcmVndWxhdG9yLW5hbWUgPSAidXNiX2hvc3RfdmJ1c19odWIiOw0K PiA+ICsJCQlyZWd1bGF0b3ItbWluLW1pY3Jvdm9sdCA9IDw1MDAwMDAwPjsNCj4gPiArCQkJcmVn dWxhdG9yLW1heC1taWNyb3ZvbHQgPSA8NTAwMDAwMD47DQo+ID4gKwkJCWdwaW8gPSA8JmdwaW8z IDI4IEdQSU9fQUNUSVZFX0hJR0g+Ow0KPiA+ICsJCQlzdGFydHVwLWRlbGF5LXVzID0gPDIwMDA+ Ow0KPiA+ICsJCQllbmFibGUtYWN0aXZlLWhpZ2g7DQo+ID4gKwkJCXN0YXR1cyA9ICJva2F5IjsN Cj4gPiArCQl9Ow0KPiA+ICsNCj4gPiArCQlyZWdfdXNiX2hvc3RfdmJ1czogdXNiX2hvc3RfdmJ1 cyB7DQo+ID4gKwkJCWNvbXBhdGlibGUgPSAicmVndWxhdG9yLWZpeGVkIjsNCj4gPiArCQkJcGlu Y3RybC1uYW1lcyA9ICJkZWZhdWx0IjsNCj4gPiArCQkJcGluY3RybC0wID0gPCZwaW5jdHJsX3Jl Z3VsYXRvcl91c2JoX3B3cj47DQo+ID4gKwkJCXJlZ3VsYXRvci1uYW1lID0gInVzYl9ob3N0X3Zi dXMiOw0KPiA+ICsJCQlyZWd1bGF0b3ItbWluLW1pY3Jvdm9sdCA9IDw1MDAwMDAwPjsNCj4gPiAr CQkJcmVndWxhdG9yLW1heC1taWNyb3ZvbHQgPSA8NTAwMDAwMD47DQo+ID4gKwkJCWdwaW8gPcKg wqA8JmdwaW8xIDAgR1BJT19BQ1RJVkVfSElHSD47DQo+ID4gKwkJCWVuYWJsZS1hY3RpdmUtaGln aDsNCj4gPiArCQkJdmluLXN1cHBseSA9IDwmcmVnX3VzYl9ob3N0X3ZidXNfaHViPjsNCj4gPiAr CQkJc3RhdHVzID0gImRpc2FibGVkIjsNCj4gPiArCQl9Ow0KPiA+ICsJfTsNCj4gPiArDQo+ID4g Kwlzb3VuZCB7DQo+ID4gKwkJY29tcGF0aWJsZSA9ICJmc2wsaW14LWF1ZGlvLXNndGw1MDAwIjsN Cj4gPiArCQltb2RlbCA9ICJpbXg2cS1hcGFsaXMtc2d0bDUwMDAiOw0KPiA+ICsJCXNzaS1jb250 cm9sbGVyID0gPCZzc2kxPjsNCj4gPiArCQlhdWRpby1jb2RlYyA9IDwmY29kZWM+Ow0KPiA+ICsJ CWF1ZGlvLXJvdXRpbmcgPQ0KPiA+ICsJCQkiTElORV9JTiIsICJMaW5lIEluIEphY2siLA0KPiA+ ICsJCQkiTUlDX0lOIiwgIk1pYyBKYWNrIiwNCj4gPiArCQkJIk1pYyBKYWNrIiwgIk1pYyBCaWFz IiwNCj4gPiArCQkJIkhlYWRwaG9uZSBKYWNrIiwgIkhQX09VVCI7DQo+ID4gKwkJbXV4LWludC1w b3J0ID0gPDE+Ow0KPiA+ICsJCW11eC1leHQtcG9ydCA9IDw0PjsNCj4gPiArCX07DQo+ID4gKw0K PiA+ICsJc291bmRfc3BkaWY6IHNvdW5kLXNwZGlmIHsNCj4gPiArCQljb21wYXRpYmxlID0gImZz bCxpbXgtYXVkaW8tc3BkaWYiOw0KPiA+ICsJCW1vZGVsID0gImlteC1zcGRpZiI7DQo+ID4gKwkJ c3BkaWYtY29udHJvbGxlciA9IDwmc3BkaWY+Ow0KPiA+ICsJCXNwZGlmLWluOw0KPiA+ICsJCXNw ZGlmLW91dDsNCj4gPiArCQlzdGF0dXMgPSAiZGlzYWJsZWQiOw0KPiA+ICsJfTsNCj4gPiArfTsN Cj4gPiArDQo+ID4gKyZhdWRtdXggew0KPiA+ICsJcGluY3RybC1uYW1lcyA9ICJkZWZhdWx0IjsN Cj4gPiArCXBpbmN0cmwtMCA9IDwmcGluY3RybF9hdWRtdXggJnBpbmN0cmxfYXVkbXV4X21jbGs+ Ow0KPiA+ICsJc3RhdHVzID0gIm9rYXkiOw0KPiA+ICt9Ow0KPiA+ICsNCj4gPiArLyogQXBhbGlz IFNQSTEgKi8NCj4gPiArJmVjc3BpMSB7DQo+ID4gKwlmc2wsc3BpLW51bS1jaGlwc2VsZWN0cyA9 IDwxPjsNCj4gPiArCWNzLWdwaW9zID0gPCZncGlvNSAyNSBHUElPX0FDVElWRV9ISUdIPjsNCj4g PiArCXBpbmN0cmwtbmFtZXMgPSAiZGVmYXVsdCI7DQo+ID4gKwlwaW5jdHJsLTAgPSA8JnBpbmN0 cmxfZWNzcGkxICZwaW5jdHJsX3NwaV9jczE+Ow0KPiA+ICsJc3RhdHVzID0gImRpc2FibGVkIjsN Cj4gPiArfTsNCj4gPiArDQo+ID4gKy8qIEFwYWxpcyBTUEkyICovDQo+ID4gKyZlY3NwaTIgew0K PiA+ICsJZnNsLHNwaS1udW0tY2hpcHNlbGVjdHMgPSA8MT47DQo+ID4gKwljcy1ncGlvcyA9IDwm Z3BpbzIgMjYgR1BJT19BQ1RJVkVfSElHSD47DQo+ID4gKwlwaW5jdHJsLW5hbWVzID0gImRlZmF1 bHQiOw0KPiA+ICsJcGluY3RybC0wID0gPCZwaW5jdHJsX2Vjc3BpMiAmcGluY3RybF9zcGlfY3My PjsNCj4gPiArCXN0YXR1cyA9ICJkaXNhYmxlZCI7DQo+ID4gK307DQo+ID4gKw0KPiA+ICsmZmVj IHsNCj4gPiArCXBpbmN0cmwtbmFtZXMgPSAiZGVmYXVsdCI7DQo+ID4gKwlwaW5jdHJsLTAgPSA8 JnBpbmN0cmxfZW5ldCAmcGluY3RybF9lbmV0X2N0cmw+Ow0KPiA+ICsJcGh5LW1vZGUgPSAicmdt aWkiOw0KPiA+ICsJcGh5LWhhbmRsZSA9IDwmZXRocGh5PjsNCj4gPiArCXBoeS1yZXNldC1kdXJh dGlvbiA9IDwxMD47DQo+ID4gKwlwaHktcmVzZXQtZ3Bpb3MgPSA8JmdwaW8xIDI1IEdQSU9fQUNU SVZFX0xPVz47DQo+ID4gKwlzdGF0dXMgPSAib2theSI7DQo+ID4gKw0KPiA+ICsJbWRpbyB7DQo+ ID4gKwkJI2FkZHJlc3MtY2VsbHMgPSA8MT47DQo+ID4gKwkJI3NpemUtY2VsbHMgPSA8MD47DQo+ ID4gKw0KPiA+ICsJCWV0aHBoeTogZXRoZXJuZXQtcGh5QDcgew0KPiA+ICsJCQlpbnRlcnJ1cHQt cGFyZW50ID0gPCZncGlvMT47DQo+ID4gKwkJCWludGVycnVwdHMgPSA8MzAgSVJRX1RZUEVfTEVW RUxfTE9XPjsNCj4gPiArCQkJcmVnID0gPDc+Ow0KPiA+ICsJCX07DQo+ID4gKwl9Ow0KPiA+ICt9 Ow0KPiA+ICsNCj4gPiArJmNhbjEgew0KPiA+ICsJcGluY3RybC1uYW1lcyA9ICJkZWZhdWx0IjsN Cj4gPiArCXBpbmN0cmwtMCA9IDwmcGluY3RybF9mbGV4Y2FuMT47DQo+ID4gKwlzdGF0dXMgPSAi ZGlzYWJsZWQiOw0KPiA+ICt9Ow0KPiA+ICsNCj4gPiArJmNhbjIgew0KPiA+ICsJcGluY3RybC1u YW1lcyA9ICJkZWZhdWx0IjsNCj4gPiArCXBpbmN0cmwtMCA9IDwmcGluY3RybF9mbGV4Y2FuMj47 DQo+ID4gKwlzdGF0dXMgPSAiZGlzYWJsZWQiOw0KPiA+ICt9Ow0KPiA+ICsNCj4gPiArJmhkbWkg ew0KPiA+ICsJZGRjLWkyYy1idXMgPSA8JmkyY2RkYz47DQo+ID4gKwlzdGF0dXMgPSAib2theSI7 DQo+ID4gK307DQo+ID4gKw0KPiA+ICsvKg0KPiA+ICsgKiBHRU4xX0kyQzogSTJDMV9TREEvU0NM IG9uIE1YTTMgMjA5LzIxMSAoZS5nLiBSVEMgb24gY2Fycmllcg0KPiA+ICsgKiBib2FyZCkNCj4g PiArICovDQo+ID4gKyZpMmMxIHsNCj4gPiArCWNsb2NrLWZyZXF1ZW5jeSA9IDwxMDAwMDA+Ow0K PiA+ICsJcGluY3RybC1uYW1lcyA9ICJkZWZhdWx0IjsNCj4gPiArCXBpbmN0cmwtMCA9IDwmcGlu Y3RybF9pMmMxPjsNCj4gPiArCXN0YXR1cyA9ICJkaXNhYmxlZCI7DQo+ID4gK307DQo+ID4gKw0K PiA+ICsmaTJjMiB7DQo+ID4gKwljbG9jay1mcmVxdWVuY3kgPSA8MTAwMDAwPjsNCj4gPiArCXBp bmN0cmwtbmFtZXMgPSAiZGVmYXVsdCI7DQo+ID4gKwlwaW5jdHJsLTAgPSA8JnBpbmN0cmxfaTJj Mj47DQo+ID4gKwlzdGF0dXMgPSAib2theSI7DQo+ID4gKw0KPiA+ICsJcG1pYzogcGZ1emUxMDBA MDggew0KPiA+ICsJCWNvbXBhdGlibGUgPSAiZnNsLHBmdXplMTAwIjsNCj4gPiArCQlyZWcgPSA8 MHgwOD47DQo+ID4gKw0KPiA+ICsJCXJlZ3VsYXRvcnMgew0KPiA+ICsJCQlzdzFhX3JlZzogc3cx YWIgew0KPiA+ICsJCQkJcmVndWxhdG9yLW1pbi1taWNyb3ZvbHQgPQ0KPiA+IDwzMDAwMDA+Ow0K PiA+ICsJCQkJcmVndWxhdG9yLW1heC1taWNyb3ZvbHQgPQ0KPiA+IDwxODc1MDAwPjsNCj4gPiAr CQkJCXJlZ3VsYXRvci1ib290LW9uOw0KPiA+ICsJCQkJcmVndWxhdG9yLWFsd2F5cy1vbjsNCj4g PiArCQkJCXJlZ3VsYXRvci1yYW1wLWRlbGF5ID0gPDYyNTA+Ow0KPiA+ICsJCQl9Ow0KPiA+ICsN Cj4gPiArCQkJc3cxY19yZWc6IHN3MWMgew0KPiA+ICsJCQkJcmVndWxhdG9yLW1pbi1taWNyb3Zv bHQgPQ0KPiA+IDwzMDAwMDA+Ow0KPiA+ICsJCQkJcmVndWxhdG9yLW1heC1taWNyb3ZvbHQgPQ0K PiA+IDwxODc1MDAwPjsNCj4gPiArCQkJCXJlZ3VsYXRvci1ib290LW9uOw0KPiA+ICsJCQkJcmVn dWxhdG9yLWFsd2F5cy1vbjsNCj4gPiArCQkJCXJlZ3VsYXRvci1yYW1wLWRlbGF5ID0gPDYyNTA+ Ow0KPiA+ICsJCQl9Ow0KPiA+ICsNCj4gPiArCQkJc3czYV9yZWc6IHN3M2Egew0KPiA+ICsJCQkJ cmVndWxhdG9yLW1pbi1taWNyb3ZvbHQgPQ0KPiA+IDw0MDAwMDA+Ow0KPiA+ICsJCQkJcmVndWxh dG9yLW1heC1taWNyb3ZvbHQgPQ0KPiA+IDwxOTc1MDAwPjsNCj4gPiArCQkJCXJlZ3VsYXRvci1i b290LW9uOw0KPiA+ICsJCQkJcmVndWxhdG9yLWFsd2F5cy1vbjsNCj4gPiArCQkJfTsNCj4gPiAr DQo+ID4gKwkJCXN3YnN0X3JlZzogc3dic3Qgew0KPiA+ICsJCQkJcmVndWxhdG9yLW1pbi1taWNy b3ZvbHQgPQ0KPiA+IDw1MDAwMDAwPjsNCj4gPiArCQkJCXJlZ3VsYXRvci1tYXgtbWljcm92b2x0 ID0NCj4gPiA8NTE1MDAwMD47DQo+ID4gKwkJCQlyZWd1bGF0b3ItYm9vdC1vbjsNCj4gPiArCQkJ CXJlZ3VsYXRvci1hbHdheXMtb247DQo+ID4gKwkJCX07DQo+ID4gKw0KPiA+ICsJCQlzbnZzX3Jl ZzogdnNudnMgew0KPiA+ICsJCQkJcmVndWxhdG9yLW1pbi1taWNyb3ZvbHQgPQ0KPiA+IDwxMDAw MDAwPjsNCj4gPiArCQkJCXJlZ3VsYXRvci1tYXgtbWljcm92b2x0ID0NCj4gPiA8MzAwMDAwMD47 DQo+ID4gKwkJCQlyZWd1bGF0b3ItYm9vdC1vbjsNCj4gPiArCQkJCXJlZ3VsYXRvci1hbHdheXMt b247DQo+ID4gKwkJCX07DQo+ID4gKw0KPiA+ICsJCQl2cmVmX3JlZzogdnJlZmRkciB7DQo+ID4g KwkJCQlyZWd1bGF0b3ItYm9vdC1vbjsNCj4gPiArCQkJCXJlZ3VsYXRvci1hbHdheXMtb247DQo+ ID4gKwkJCX07DQo+ID4gKw0KPiA+ICsJCQl2Z2VuMV9yZWc6IHZnZW4xIHsNCj4gPiArCQkJCXJl Z3VsYXRvci1taW4tbWljcm92b2x0ID0NCj4gPiA8ODAwMDAwPjsNCj4gPiArCQkJCXJlZ3VsYXRv ci1tYXgtbWljcm92b2x0ID0NCj4gPiA8MTU1MDAwMD47DQo+ID4gKwkJCQlyZWd1bGF0b3ItYm9v dC1vbjsNCj4gPiArCQkJCXJlZ3VsYXRvci1hbHdheXMtb247DQo+ID4gKwkJCX07DQo+ID4gKw0K PiA+ICsJCQl2Z2VuMl9yZWc6IHZnZW4yIHsNCj4gPiArCQkJCXJlZ3VsYXRvci1taW4tbWljcm92 b2x0ID0NCj4gPiA8ODAwMDAwPjsNCj4gPiArCQkJCXJlZ3VsYXRvci1tYXgtbWljcm92b2x0ID0N Cj4gPiA8MTU1MDAwMD47DQo+ID4gKwkJCQlyZWd1bGF0b3ItYm9vdC1vbjsNCj4gPiArCQkJCXJl Z3VsYXRvci1hbHdheXMtb247DQo+ID4gKwkJCX07DQo+ID4gKw0KPiA+ICsJCQl2Z2VuM19yZWc6 IHZnZW4zIHsNCj4gPiArCQkJCXJlZ3VsYXRvci1taW4tbWljcm92b2x0ID0NCj4gPiA8MTgwMDAw MD47DQo+ID4gKwkJCQlyZWd1bGF0b3ItbWF4LW1pY3Jvdm9sdCA9DQo+ID4gPDMzMDAwMDA+Ow0K PiA+ICsJCQkJcmVndWxhdG9yLWJvb3Qtb247DQo+ID4gKwkJCQlyZWd1bGF0b3ItYWx3YXlzLW9u Ow0KPiA+ICsJCQl9Ow0KPiA+ICsNCj4gPiArCQkJdmdlbjRfcmVnOiB2Z2VuNCB7DQo+ID4gKwkJ CQlyZWd1bGF0b3ItbWluLW1pY3Jvdm9sdCA9DQo+ID4gPDE4MDAwMDA+Ow0KPiA+ICsJCQkJcmVn dWxhdG9yLW1heC1taWNyb3ZvbHQgPQ0KPiA+IDwzMzAwMDAwPjsNCj4gPiArCQkJCXJlZ3VsYXRv ci1ib290LW9uOw0KPiA+ICsJCQkJcmVndWxhdG9yLWFsd2F5cy1vbjsNCj4gPiArCQkJfTsNCj4g PiArDQo+ID4gKwkJCXZnZW41X3JlZzogdmdlbjUgew0KPiA+ICsJCQkJcmVndWxhdG9yLW1pbi1t aWNyb3ZvbHQgPQ0KPiA+IDwxODAwMDAwPjsNCj4gPiArCQkJCXJlZ3VsYXRvci1tYXgtbWljcm92 b2x0ID0NCj4gPiA8MzMwMDAwMD47DQo+ID4gKwkJCQlyZWd1bGF0b3ItYm9vdC1vbjsNCj4gPiAr CQkJCXJlZ3VsYXRvci1hbHdheXMtb247DQo+ID4gKwkJCX07DQo+ID4gKw0KPiA+ICsJCQl2Z2Vu Nl9yZWc6IHZnZW42IHsNCj4gPiArCQkJCXJlZ3VsYXRvci1taW4tbWljcm92b2x0ID0NCj4gPiA8 MTgwMDAwMD47DQo+ID4gKwkJCQlyZWd1bGF0b3ItbWF4LW1pY3Jvdm9sdCA9DQo+ID4gPDMzMDAw MDA+Ow0KPiA+ICsJCQkJcmVndWxhdG9yLWJvb3Qtb247DQo+ID4gKwkJCQlyZWd1bGF0b3ItYWx3 YXlzLW9uOw0KPiA+ICsJCQl9Ow0KPiA+ICsJCX07DQo+ID4gKwl9Ow0KPiA+ICsNCj4gPiArCWNv ZGVjOiBzZ3RsNTAwMEAwYSB7DQo+ID4gKwkJY29tcGF0aWJsZSA9ICJmc2wsc2d0bDUwMDAiOw0K PiA+ICsJCXJlZyA9IDwweDBhPjsNCj4gPiArCQljbG9ja3MgPSA8JmNsa3MgMjAxPjsNCj4gPiAr CQlWRERBLXN1cHBseSA9IDwmcmVnXzJwNXY+Ow0KPiA+ICsJCVZERElPLXN1cHBseSA9IDwmcmVn XzNwM3Y+Ow0KPiANCj4gTml0OiBUaGUgZGV2aWNlIHRyZWUgYmluZGluZ3MgbWVudGlvbiB0d28g bW9yZSBwcm9wZXJ0aWVzIGFzIHJlcXVpcmVkDQo+IHByb3BlcnRpZXM6DQo+IG1pY2JpYXMtcmVz aXN0b3Itay1vaG1zDQo+IG1pY2JpYXMtdm9sdGFnZS1tLXZvbHRzDQo+IA0KPiBIb3dldmVyLCBi b3RoIGhhdmUgIklmIHRoaXMgbm9kZSBpcyBub3QgbWVudGlvbmVkIiwgaGVuY2UgSSBndWVzcw0K PiB0aGV5DQo+IGFyZSBhY3R1YWxseSBvcHRpb25hbCwgYnV0IG1heWJlIHdlIHdhbnQgdG8gc2V0 IGFuIGV4cGxpY2l0IHZhbHVlDQo+IGhlcmU/DQoNClJlbWVtYmVyIHdlIGRvbid0IG1ha2UgdXNl IG9mIGFueSBvZiB0aGF0IG1pY3JvcGhvbmUgYmlhcyBzdHVmZiBvbiBhbnkNCm9mIG91ciBBcGFs aXMgaGFyZHdhcmUuDQoNCj4gPiArCX07DQo+ID4gKw0KPiA+ICsJLyogU1RNUEU4MTEgdG91Y2gg c2NyZWVuIGNvbnRyb2xsZXIgKi8NCj4gPiArCXN0bXBlODExQDQxIHsNCj4gPiArCQljb21wYXRp YmxlID0gInN0LHN0bXBlODExIjsNCj4gPiArCQlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOw0K PiA+ICsJCXBpbmN0cmwtMCA9IDwmcGluY3RybF90b3VjaF9pbnQ+Ow0KPiA+ICsJCSNhZGRyZXNz LWNlbGxzID0gPDE+Ow0KPiA+ICsJCSNzaXplLWNlbGxzID0gPDA+Ow0KPiA+ICsJCXJlZyA9IDww eDQxPjsNCj4gPiArCQlpbnRlcnJ1cHRzID0gPDEwIElSUV9UWVBFX0xFVkVMX0xPVz47DQo+ID4g KwkJaW50ZXJydXB0LXBhcmVudCA9IDwmZ3BpbzQ+Ow0KPiA+ICsJCWludGVycnVwdC1jb250cm9s bGVyOw0KPiA+ICsJCWlkID0gPDA+Ow0KPiA+ICsJCWJsb2NrcyA9IDwweDU+Ow0KPiA+ICsJCWly cS10cmlnZ2VyID0gPDB4MT47DQo+ID4gKwkJc3RtcGVfdG91Y2hzY3JlZW4gew0KPiA+ICsJCQlj b21wYXRpYmxlID0gInN0LHN0bXBlLXRzIjsNCj4gPiArCQkJcmVnID0gPDA+Ow0KPiA+ICsJCQkv KiAzLjI1IE1IeiBBREMgY2xvY2sgc3BlZWQgKi8NCj4gPiArCQkJc3QsYWRjLWZyZXEgPSA8MT47 DQo+ID4gKwkJCS8qIDggc2FtcGxlIGF2ZXJhZ2UgY29udHJvbCAqLw0KPiA+ICsJCQlzdCxhdmUt Y3RybCA9IDwzPjsNCj4gPiArCQkJLyogNyBsZW5ndGggZnJhY3Rpb25hbCBwYXJ0IGluIHogKi8N Cj4gPiArCQkJc3QsZnJhY3Rpb24teiA9IDw3PjsNCj4gPiArCQkJLyoNCj4gPiArCQkJwqAqIDUw IG1BIHR5cGljYWwgODAgbUEgbWF4IHRvdWNoc2NyZWVuDQo+ID4gZHJpdmVycw0KPiA+ICsJCQnC oCogY3VycmVudCBsaW1pdCB2YWx1ZQ0KPiA+ICsJCQnCoCovDQo+ID4gKwkJCXN0LGktZHJpdmUg PSA8MT47DQo+ID4gKwkJCS8qIDEyLWJpdCBBREMgKi8NCj4gPiArCQkJc3QsbW9kLTEyYiA9IDwx PjsNCj4gPiArCQkJLyogaW50ZXJuYWwgQURDIHJlZmVyZW5jZSAqLw0KPiA+ICsJCQlzdCxyZWYt c2VsID0gPDA+Ow0KPiA+ICsJCQkvKiBBREMgY29udmVyc3Rpb24gdGltZTogODAgY2xvY2tzICov DQo+ID4gKwkJCXN0LHNhbXBsZS10aW1lID0gPDQ+Ow0KPiA+ICsJCQkvKiAxIG1zIHBhbmVsIGRy aXZlciBzZXR0bGluZyB0aW1lICovDQo+ID4gKwkJCXN0LHNldHRsaW5nID0gPDM+Ow0KPiA+ICsJ CQkvKiA1IG1zIHRvdWNoIGRldGVjdCBpbnRlcnJ1cHQgZGVsYXkgKi8NCj4gPiArCQkJc3QsdG91 Y2gtZGV0LWRlbGF5ID0gPDU+Ow0KPiA+ICsJCX07DQo+ID4gKwl9Ow0KPiA+ICt9Ow0KPiA+ICsN Cj4gPiArLyoNCj4gPiArICogR0VOMl9JMkMsIENBTTogSTJDM19TREEvU0NMIG9uIE1YTTMgMjAx LzIwMyAodW51c2VkKQ0KPiA+ICsgKi8NCj4gPiArJmkyYzMgew0KPiA+ICsJY2xvY2stZnJlcXVl bmN5ID0gPDEwMDAwMD47DQo+ID4gKwlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiLCAicmVjb3Zl cnkiOw0KPiA+ICsJcGluY3RybC0wID0gPCZwaW5jdHJsX2kyYzM+Ow0KPiA+ICsJcGluY3RybC0x ID0gPCZwaW5jdHJsX2kyYzNfcmVjb3Zlcnk+Ow0KPiA+ICsJc2NsLWdwaW9zID0gPCZncGlvMyAx NyBHUElPX0FDVElWRV9ISUdIPjsNCj4gPiArCXNkYS1ncGlvcyA9IDwmZ3BpbzMgMTggR1BJT19B Q1RJVkVfSElHSD47DQo+ID4gKwlzdGF0dXMgPSAiZGlzYWJsZWQiOw0KPiA+ICt9Ow0KPiA+ICsN Cj4gPiArLyogUEFEIEN0cmwgdmFsdWVzIGZvciBjb21tb24gc2V0dGluZ3MgKi8NCj4gPiArLyoN Cj4gPiArICogKFBBRF9DVExfSFlTIHwgUEFEX0NUTF9QVVNfMTAwS19VUCB8IFBBRF9DVExfUFVF IHwgUEFEX0NUTF9QS0UNCj4gPiB8DQo+ID4gKyAqwqDCoFBBRF9DVExfU1BFRURfTUVEIHwgUEFE X0NUTF9EU0VfNDBvaG0pDQo+ID4gKyAqLw0KPiA+ICsjZGVmaW5lIFBBRF9DVFJMX0hZU19QVSAw eDFiMGIwDQo+ID4gKw0KPiA+ICsvKg0KPiA+ICsgKiAoUEFEX0NUTF9IWVMgfCBQQURfQ1RMX1BV RSB8IFBBRF9DVExfUEtFIHwgUEFEX0NUTF9TUEVFRF9NRUQgfA0KPiA+ICsgKsKgwqBQQURfQ1RM X0RTRV80MG9obSkNCj4gPiArICovDQo+ID4gKyNkZWZpbmUgUEFEX0NUUkxfSFlTX1BEIDB4MTMw YjANCj4gPiArDQo+ID4gKy8qDQo+ID4gKyAqIChQQURfQ1RMX1BVU18yMktfVVAgfCBQQURfQ1RM X1BVRSB8IFBBRF9DVExfUEtFIHwNCj4gPiBQQURfQ1RMX1NQRUVEX0xPVyB8DQo+ID4gKyAqwqDC oFBBRF9DVExfRFNFXzgwb2htKQ0KPiA+ICsgKi8NCj4gPiArI2RlZmluZSBQQURfQ1RSTF9QVV8y MmsgMHgwZjA1OA0KPiA+ICsNCj4gPiArJmlvbXV4YyB7DQo+IA0KPiBJIHRoaW5rIGl0IGlzIGEg Y29udmVudGlvbiB0byBtb3ZlIGlvbXV4YyBhdCB0aGUgdmVyeSBlbmQgZm9yIGJldHRlcg0KPiBy ZWFkYWJpbGl0eSBvZiB0aGUgcmVzdC4gQXQgbGVhc3QgdGhlIFZ5YnJpZCBkdHMgYW5kIHRoZSBt b3JlDQo+IHJlY2VudGx5DQo+IGFkZGVkIGlteDdkLXNkYi5kdHMgZm9sbG93IHRoaXMgcnVsZS4N Cg0KWWVzLCB3aGlsZSB0aGUgVGVncmFzIGhhdmUgaXQgYXQgdGhlIGJlZ2lubmluZyBOWFAgd2Fu dHMgaXQgYXQgdGhlIGVuZA0KKDstcCkuDQoNCj4gPiArCWVjc3BpIHsNCj4gPiArCQlwaW5jdHJs X2Vjc3BpMTogZWNzcGkxZ3JwIHsNCj4gPiArCQkJZnNsLHBpbnMgPSA8DQo+ID4gKwkJCQlNWDZR RExfUEFEX0NTSTBfREFUNl9fRUNTUEkxX01JU08NCj4gPiAweDEwMGIxDQo+ID4gKwkJCQlNWDZR RExfUEFEX0NTSTBfREFUNV9fRUNTUEkxX01PU0kNCj4gPiAweDEwMGIxDQo+ID4gKwkJCQlNWDZR RExfUEFEX0NTSTBfREFUNF9fRUNTUEkxX1NDTEsNCj4gPiAweDEwMGIxDQo+ID4gKwkJCT47DQo+ ID4gKwkJfTsNCj4gPiArCQlwaW5jdHJsX2Vjc3BpMjogZWNzcGkyZ3JwIHsNCj4gPiArCQkJZnNs LHBpbnMgPSA8DQo+ID4gKwkJCQlNWDZRRExfUEFEX0VJTV9PRV9fRUNTUEkyX01JU08NCj4gPiAw eDEwMGIxDQo+ID4gKwkJCQlNWDZRRExfUEFEX0VJTV9DUzFfX0VDU1BJMl9NT1NJDQo+ID4gMHgx MDBiMQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9FSU1fQ1MwX19FQ1NQSTJfU0NMSw0KPiA+IDB4MTAw YjENCj4gPiArCQkJPjsNCj4gPiArCQl9Ow0KPiA+ICsJCXBpbmN0cmxfc3BpX2NzMTogc3BpX2Nz MSB7DQo+ID4gKwkJCWZzbCxwaW5zID0gPA0KPiA+ICsJCQkJLyogU1BJMSBjcyAqLw0KPiA+ICsJ CQkJTVg2UURMX1BBRF9DU0kwX0RBVDdfX0dQSU81X0lPMjUJDQo+ID4gMHgwMDBiMQ0KPiA+ICsJ CQk+Ow0KPiA+ICsJCX07DQo+ID4gKwkJcGluY3RybF9zcGlfY3MyOiBzcGlfY3MyIHsNCj4gPiAr CQkJZnNsLHBpbnMgPSA8DQo+ID4gKwkJCQkvKiBTUEkyIGNzICovDQo+ID4gKwkJCQlNWDZRRExf UEFEX0VJTV9SV19fR1BJTzJfSU8yNgkNCj4gPiAJMHgwMDBiMQ0KPiA+ICsJCQk+Ow0KPiA+ICsJ CX07DQo+ID4gKwl9Ow0KPiA+ICsNCj4gPiArCWZsZXhjYW4gew0KPiA+ICsJCXBpbmN0cmxfZmxl eGNhbjE6IGZsZXhjYW4xZ3JwIHsNCj4gPiArCQkJZnNsLHBpbnMgPSA8DQo+ID4gKwkJCQlNWDZR RExfUEFEX0dQSU9fN19fRkxFWENBTjFfVFgNCj4gPiAweDFiMGIwDQo+ID4gKwkJCQlNWDZRRExf UEFEX0dQSU9fOF9fRkxFWENBTjFfUlgNCj4gPiAweDFiMGIwDQo+ID4gKwkJCT47DQo+ID4gKwkJ fTsNCj4gPiArCQlwaW5jdHJsX2ZsZXhjYW4yOiBmbGV4Y2FuMmdycCB7DQo+ID4gKwkJCWZzbCxw aW5zID0gPA0KPiA+ICsJCQkJTVg2UURMX1BBRF9LRVlfQ09MNF9fRkxFWENBTjJfVFgNCj4gPiAw eDFiMGIwDQo+ID4gKwkJCQlNWDZRRExfUEFEX0tFWV9ST1c0X19GTEVYQ0FOMl9SWA0KPiA+IDB4 MWIwYjANCj4gPiArCQkJPjsNCj4gPiArCQl9Ow0KPiA+ICsJfTsNCj4gPiArDQo+ID4gKwlncGlv IHsNCj4gPiArCQlwaW5jdHJsX2FwYWxpc19ncGlvMTogYXBhbGlzX2dwaW8xIHsNCj4gPiArCQkJ ZnNsLHBpbnMgPSA8DQo+ID4gKwkJCQlNWDZRRExfUEFEX05BTkRGX0Q0X19HUElPMl9JTzA0DQo+ ID4gUEFEX0NUUkxfSFlTX1BEDQo+ID4gKwkJCT47DQo+ID4gKwkJfTsNCj4gPiArCQlwaW5jdHJs X2FwYWxpc19ncGlvMjogYXBhbGlzX2dwaW8yIHsNCj4gPiArCQkJZnNsLHBpbnMgPSA8DQo+ID4g KwkJCQlNWDZRRExfUEFEX05BTkRGX0Q1X19HUElPMl9JTzA1DQo+ID4gUEFEX0NUUkxfSFlTX1BE DQo+ID4gKwkJCT47DQo+ID4gKwkJfTsNCj4gPiArCQlwaW5jdHJsX2FwYWxpc19ncGlvMzogYXBh bGlzX2dwaW8zIHsNCj4gPiArCQkJZnNsLHBpbnMgPSA8DQo+ID4gKwkJCQlNWDZRRExfUEFEX05B TkRGX0Q2X19HUElPMl9JTzA2DQo+ID4gUEFEX0NUUkxfSFlTX1BEDQo+ID4gKwkJCT47DQo+ID4g KwkJfTsNCj4gPiArCQlwaW5jdHJsX2FwYWxpc19ncGlvNDogYXBhbGlzX2dwaW80IHsNCj4gPiAr CQkJZnNsLHBpbnMgPSA8DQo+ID4gKwkJCQlNWDZRRExfUEFEX05BTkRGX0Q3X19HUElPMl9JTzA3 DQo+ID4gUEFEX0NUUkxfSFlTX1BEDQo+ID4gKwkJCT47DQo+ID4gKwkJfTsNCj4gPiArCQlwaW5j dHJsX2FwYWxpc19ncGlvNTogYXBhbGlzX2dwaW81IHsNCj4gPiArCQkJZnNsLHBpbnMgPSA8DQo+ ID4gKwkJCQlNWDZRRExfUEFEX05BTkRGX1JCMF9fR1BJTzZfSU8xMA0KPiA+IFBBRF9DVFJMX0hZ U19QRA0KPiA+ICsJCQk+Ow0KPiA+ICsJCX07DQo+ID4gKwkJcGluY3RybF9hcGFsaXNfZ3BpbzY6 IGFwYWxpc19ncGlvNiB7DQo+ID4gKwkJCWZzbCxwaW5zID0gPA0KPiA+ICsJCQkJTVg2UURMX1BB RF9OQU5ERl9XUF9CX19HUElPNl9JTzA5DQo+ID4gKwkJCQkJCVBBRF9DVFJMX0hZU19QRA0KPiAN Cj4gVGhlIDgwIGNoYXJhY3RlciBsaW1pdCBub3JtYWxseSBpcyBub3QgZW5mb3JjZWQgZm9yIGRl dmljZSB0cmVlcywNCj4gaGVuY2UNCj4gSSB3b3VsZCByZW1vdmUgdGhhdCBsaW5lIGJyZWFrIGhl cmUuLi4NCg0KWWVzLCBhbmQgdGhlbiB0cnlpbmcgdG8gdGVhY2ggcGF0bWFuIHRvIGFjdHVhbGx5 IGlnbm9yZSB0aGF0IHdhcm5pbmcNCig7LXApLg0KDQo+ID4gKwkJCT47DQo+ID4gKwkJfTsNCj4g PiArCQlwaW5jdHJsX2FwYWxpc19ncGlvNzogYXBhbGlzX2dwaW83IHsNCj4gPiArCQkJZnNsLHBp bnMgPSA8DQo+ID4gKwkJCQlNWDZRRExfUEFEX0dQSU9fMl9fR1BJTzFfSU8wMg0KPiA+IFBBRF9D VFJMX0hZU19QRA0KPiA+ICsJCQk+Ow0KPiA+ICsJCX07DQo+ID4gKwkJcGluY3RybF9hcGFsaXNf Z3Bpbzg6IGFwYWxpc19ncGlvOCB7DQo+ID4gKwkJCWZzbCxwaW5zID0gPA0KPiA+ICsJCQkJTVg2 UURMX1BBRF9HUElPXzZfX0dQSU8xX0lPMDYNCj4gPiBQQURfQ1RSTF9IWVNfUEQNCj4gPiArCQkJ PjsNCj4gPiArCQl9Ow0KPiA+ICsJCXBpbmN0cmxfZ3Bpb19rZXlzOiBncGlvX2tleXMgew0KPiA+ ICsJCQlmc2wscGlucyA9IDwNCj4gPiArCQkJCS8qIFBvd2VyIEJ1dHRvbiAqLw0KPiA+ICsJCQkJ TVg2UURMX1BBRF9HUElPXzRfX0dQSU8xX0lPMDQNCj4gPiBQQURfQ1RSTF9IWVNfUFUNCj4gPiAr CQkJPjsNCj4gPiArCQl9Ow0KPiA+ICsJfTsNCj4gPiArDQo+ID4gKwloZG1pIHsNCj4gPiArCQlw aW5jdHJsX2hkbWlfY2VjOiBoZG1pY2VjZ3JwIHsNCj4gPiArCQkJZnNsLHBpbnMgPSA8DQo+ID4g KwkJCQlNWDZRRExfUEFEX0tFWV9ST1cyX19IRE1JX1RYX0NFQ19MDQo+ID4gSU5FIDB4MWY4YjAN Cj4gPiArCQkJPjsNCj4gPiArCQl9Ow0KPiA+ICsJfTsNCj4gPiArDQo+ID4gKwlpMmMgew0KPiA+ ICsJCXBpbmN0cmxfaTJjX2RkYzogaTJjX2RkYyB7DQo+ID4gKwkJCWZzbCxwaW5zID0gPA0KPiA+ ICsJCQkJLyogRERDIGJpdGJhbmcgKi8NCj4gPiArCQkJCU1YNlFETF9QQURfRUlNX0VCMl9fR1BJ TzJfSU8zMA0KPiA+IFBBRF9DVFJMX0hZU19QVQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9FSU1fRDE2 X19HUElPM19JTzE2DQo+ID4gUEFEX0NUUkxfSFlTX1BVDQo+ID4gKwkJCT47DQo+ID4gKwkJfTsN Cj4gPiArCQlwaW5jdHJsX2kyYzE6IGkyYzFncnAgew0KPiA+ICsJCQlmc2wscGlucyA9IDwNCj4g PiArCQkJCU1YNlFETF9QQURfQ1NJMF9EQVQ4X19JMkMxX1NEQQ0KPiA+IDB4NDAwMWI4YjENCj4g PiArCQkJCU1YNlFETF9QQURfQ1NJMF9EQVQ5X19JMkMxX1NDTA0KPiA+IDB4NDAwMWI4YjENCj4g PiArCQkJPjsNCj4gPiArCQl9Ow0KPiA+ICsJCXBpbmN0cmxfaTJjMzogaTJjM2dycCB7DQo+ID4g KwkJCWZzbCxwaW5zID0gPA0KPiA+ICsJCQkJTVg2UURMX1BBRF9FSU1fRDE3X19JMkMzX1NDTA0K PiA+IDB4NDAwMWI4YjENCj4gPiArCQkJCU1YNlFETF9QQURfRUlNX0QxOF9fSTJDM19TREENCj4g PiAweDQwMDFiOGIxDQo+ID4gKwkJCT47DQo+ID4gKwkJfTsNCj4gPiArCQlwaW5jdHJsX2kyYzNf cmVjb3Zlcnk6IGkyYzMtcmVjb3ZlcnlncnAgew0KPiA+ICsJCQlmc2wscGlucyA9IDwNCj4gPiAr CQkJCU1YNlFETF9QQURfRUlNX0QxN19fR1BJTzNfSU8xNw0KPiA+IDB4NDAwMWI4YjENCj4gPiAr CQkJCU1YNlFETF9QQURfRUlNX0QxOF9fR1BJTzNfSU8xOA0KPiA+IDB4NDAwMWI4YjENCj4gPiAr CQkJPjsNCj4gPiArCQl9Ow0KPiA+ICsJfTsNCj4gPiArDQo+ID4gKwkvKiBwaW5zIHVzZWQgb24g bW9kdWxlICovDQo+ID4gKwlpbXg2cS1hcGFsaXMgew0KPiA+ICsJCXBpbmN0cmwtbmFtZXMgPSAi ZGVmYXVsdCI7DQo+ID4gKwkJcGluY3RybC0wID0gPCZwaW5jdHJsX3Jlc2V0X21vY2kNCj4gPiAm cGluY3RybF9lbW1jX3Jlc2V0PjsNCj4gPiArCQlwaW5jdHJsX2F1ZG11eDogYXVkbXV4Z3JwIHsN Cj4gPiArCQkJZnNsLHBpbnMgPSA8DQo+ID4gKwkJCQlNWDZRRExfUEFEX0RJU1AwX0RBVDIwX19B VUQ0X1RYQwkNCj4gPiAweDEzMGIwDQo+ID4gKwkJCQlNWDZRRExfUEFEX0RJU1AwX0RBVDIxX19B VUQ0X1RYRAkNCj4gPiAweDEzMGIwDQo+ID4gKwkJCQlNWDZRRExfUEFEX0RJU1AwX0RBVDIyX19B VUQ0X1RYRlMJDQo+ID4gMHgxMzBiMA0KPiA+ICsJCQkJTVg2UURMX1BBRF9ESVNQMF9EQVQyM19f QVVENF9SWEQJDQo+ID4gMHgxMzBiMA0KPiA+ICsJCQk+Ow0KPiA+ICsJCX07DQo+ID4gKwkJcGlu Y3RybF9hdWRtdXhfbWNsazogYXVkbXV4X21jbGsgew0KPiA+ICsJCQlmc2wscGlucyA9IDwNCj4g PiArCQkJCS8qIFNHVEw1MDAwIHN5c19tY2xrICovDQo+ID4gKwkJCQlNWDZRRExfUEFEX0dQSU9f NV9fQ0NNX0NMS08xDQo+ID4gMHgxMzBiMA0KPiA+ICsJCQk+Ow0KPiA+ICsJCX07DQo+ID4gKwkJ cGluY3RybF9lbW1jX3Jlc2V0OiBlbW1jX3Jlc2V0IHsNCj4gPiArCQkJZnNsLHBpbnMgPSA8DQo+ ID4gKwkJCQkvKiBlTU1DIHJlc2V0LCBsZWF2ZSBpdCBhbG9uZSAqLw0KPiA+ICsJCQkJTVg2UURM X1BBRF9TRDNfUlNUX19HUElPN19JTzA4DQo+ID4gUEFEX0NUUkxfUFVfMjJrDQo+ID4gKwkJCT47 DQo+ID4gKwkJfTsNCj4gPiArCQlwaW5jdHJsX2VuZXQ6IGVuZXRncnAgew0KPiA+ICsJCQlmc2ws cGlucyA9IDwNCj4gPiArCQkJCU1YNlFETF9QQURfRU5FVF9NRElPX19FTkVUX01ESU8JDQo+ID4g CTB4MTAwYjANCj4gPiArCQkJCU1YNlFETF9QQURfRU5FVF9NRENfX0VORVRfTURDCQ0KPiA+IAkw eDEwMGIwDQo+ID4gKwkJCQlNWDZRRExfUEFEX1JHTUlJX1RYQ19fUkdNSUlfVFhDCQ0KPiA+IAkw eDEwMGIwDQo+ID4gKwkJCQlNWDZRRExfUEFEX1JHTUlJX1REMF9fUkdNSUlfVEQwCQ0KPiA+IAkw eDEwMGIwDQo+ID4gKwkJCQlNWDZRRExfUEFEX1JHTUlJX1REMV9fUkdNSUlfVEQxCQ0KPiA+IAkw eDEwMGIwDQo+ID4gKwkJCQlNWDZRRExfUEFEX1JHTUlJX1REMl9fUkdNSUlfVEQyCQ0KPiA+IAkw eDEwMGIwDQo+ID4gKwkJCQlNWDZRRExfUEFEX1JHTUlJX1REM19fUkdNSUlfVEQzCQ0KPiA+IAkw eDEwMGIwDQo+ID4gKwkJCQlNWDZRRExfUEFEX1JHTUlJX1RYX0NUTF9fUkdNSUlfVFhfDQo+ID4g Q1RMCTB4MTAwYjANCj4gPiArCQkJCU1YNlFETF9QQURfRU5FVF9SRUZfQ0xLX19FTkVUX1RYX0MN Cj4gPiBMSwkweDEwMGIwDQo+ID4gKwkJCQlNWDZRRExfUEFEX1JHTUlJX1JYQ19fUkdNSUlfUlhD CQ0KPiA+IAkweDFiMGIwDQo+ID4gKwkJCQlNWDZRRExfUEFEX1JHTUlJX1JEMF9fUkdNSUlfUkQw CQ0KPiA+IAkweDFiMGIwDQo+ID4gKwkJCQlNWDZRRExfUEFEX1JHTUlJX1JEMV9fUkdNSUlfUkQx CQ0KPiA+IAkweDFiMGIwDQo+ID4gKwkJCQlNWDZRRExfUEFEX1JHTUlJX1JEMl9fUkdNSUlfUkQy CQ0KPiA+IAkweDFiMGIwDQo+ID4gKwkJCQlNWDZRRExfUEFEX1JHTUlJX1JEM19fUkdNSUlfUkQz CQ0KPiA+IAkweDFiMGIwDQo+ID4gKwkJCQlNWDZRRExfUEFEX1JHTUlJX1JYX0NUTF9fUkdNSUlf UlhfDQo+ID4gQ1RMCTB4MWIwYjANCj4gPiArCQkJPjsNCj4gPiArCQl9Ow0KPiA+ICsJCXBpbmN0 cmxfZW5ldF9jdHJsOiBlbmV0X2N0cmxncnAgew0KPiA+ICsJCQlmc2wscGlucyA9IDwNCj4gPiAr CQkJCS8qIEV0aGVybmV0IFBIWSByZXNldCAqLw0KPiA+ICsJCQkJTVg2UURMX1BBRF9FTkVUX0NS U19EVl9fR1BJTzFfSU8yNQ0KPiA+IAkweDAwMGIwDQo+ID4gKwkJCQkvKiBFdGhlcm5ldCBQSFkg aW50ZXJydXB0ICovDQo+ID4gKwkJCQlNWDZRRExfUEFEX0VORVRfVFhEMF9fR1BJTzFfSU8zMAkN Cj4gPiAweDAwMGIxDQo+ID4gKwkJCT47DQo+ID4gKwkJfTsNCj4gPiArCQlwaW5jdHJsX2kyYzI6 IGkyYzJncnAgew0KPiA+ICsJCQlmc2wscGlucyA9IDwNCj4gPiArCQkJCU1YNlFETF9QQURfS0VZ X0NPTDNfX0kyQzJfU0NMDQo+ID4gMHg0MDAxYjhiMQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9LRVlf Uk9XM19fSTJDMl9TREENCj4gPiAweDQwMDFiOGIxDQo+ID4gKwkJCT47DQo+ID4gKwkJfTsNCj4g PiArCQlwaW5jdHJsX2lwdTJfdmRhYzogaXB1MnZkYWNncnAgew0KPiA+ICsJCQlmc2wscGlucyA9 IDwNCj4gPiArCQkJCU1YNlFETF9QQURfREkwX0RJU1BfQ0xLX19JUFUyX0RJMF8NCj4gPiBESVNQ X0NMSyAweGQxDQo+ID4gKwkJCQlNWDZRRExfUEFEX0RJMF9QSU4xNV9fSVBVMl9ESTBfUElODQo+ ID4gMTXCoMKgwqDCoMKgwqDCoDB4ZDENCj4gPiArCQkJCU1YNlFETF9QQURfREkwX1BJTjJfX0lQ VTJfREkwX1BJTjANCj4gPiAywqDCoMKgwqDCoMKgwqDCoDB4ZDENCj4gPiArCQkJCU1YNlFETF9Q QURfREkwX1BJTjNfX0lQVTJfREkwX1BJTjANCj4gPiAzwqDCoMKgwqDCoMKgwqDCoDB4ZDENCj4g PiArCQkJCU1YNlFETF9QQURfRElTUDBfREFUMF9fSVBVMl9ESVNQMF8NCj4gPiBEQVRBMDDCoMKg wqAweGY5DQo+ID4gKwkJCQlNWDZRRExfUEFEX0RJU1AwX0RBVDFfX0lQVTJfRElTUDBfDQo+ID4g REFUQTAxwqDCoMKgMHhmOQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9ESVNQMF9EQVQyX19JUFUyX0RJ U1AwXw0KPiA+IERBVEEwMsKgwqDCoDB4ZjkNCj4gPiArCQkJCU1YNlFETF9QQURfRElTUDBfREFU M19fSVBVMl9ESVNQMF8NCj4gPiBEQVRBMDPCoMKgwqAweGY5DQo+ID4gKwkJCQlNWDZRRExfUEFE X0RJU1AwX0RBVDRfX0lQVTJfRElTUDBfDQo+ID4gREFUQTA0wqDCoMKgMHhmOQ0KPiA+ICsJCQkJ TVg2UURMX1BBRF9ESVNQMF9EQVQ1X19JUFUyX0RJU1AwXw0KPiA+IERBVEEwNcKgwqDCoDB4ZjkN Cj4gPiArCQkJCU1YNlFETF9QQURfRElTUDBfREFUNl9fSVBVMl9ESVNQMF8NCj4gPiBEQVRBMDbC oMKgwqAweGY5DQo+ID4gKwkJCQlNWDZRRExfUEFEX0RJU1AwX0RBVDdfX0lQVTJfRElTUDBfDQo+ ID4gREFUQTA3wqDCoMKgMHhmOQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9ESVNQMF9EQVQ4X19JUFUy X0RJU1AwXw0KPiA+IERBVEEwOMKgwqDCoDB4ZjkNCj4gPiArCQkJCU1YNlFETF9QQURfRElTUDBf REFUOV9fSVBVMl9ESVNQMF8NCj4gPiBEQVRBMDnCoMKgwqAweGY5DQo+ID4gKwkJCQlNWDZRRExf UEFEX0RJU1AwX0RBVDEwX19JUFUyX0RJU1AwDQo+ID4gX0RBVEExMMKgwqAweGY5DQo+ID4gKwkJ CQlNWDZRRExfUEFEX0RJU1AwX0RBVDExX19JUFUyX0RJU1AwDQo+ID4gX0RBVEExMcKgwqAweGY5 DQo+ID4gKwkJCQlNWDZRRExfUEFEX0RJU1AwX0RBVDEyX19JUFUyX0RJU1AwDQo+ID4gX0RBVEEx MsKgwqAweGY5DQo+ID4gKwkJCQlNWDZRRExfUEFEX0RJU1AwX0RBVDEzX19JUFUyX0RJU1AwDQo+ ID4gX0RBVEExM8KgwqAweGY5DQo+ID4gKwkJCQlNWDZRRExfUEFEX0RJU1AwX0RBVDE0X19JUFUy X0RJU1AwDQo+ID4gX0RBVEExNMKgwqAweGY5DQo+ID4gKwkJCQlNWDZRRExfUEFEX0RJU1AwX0RB VDE1X19JUFUyX0RJU1AwDQo+ID4gX0RBVEExNcKgwqAweGY5DQo+ID4gKwkJCT47DQo+ID4gKwkJ fTsNCj4gPiArCQlwaW5jdHJsX3JlZ3VsYXRvcl91c2JodWJfcHdyOg0KPiA+IGdwaW9fcmVndWxh dG9yX3VzYmh1Yl9wd3Igew0KPiA+ICsJCQlmc2wscGlucyA9IDwNCj4gPiArCQkJCS8qIFVTQkhf SFVCX0VOICovDQo+ID4gKwkJCQlNWDZRRExfUEFEX0VJTV9EMjhfX0dQSU8zX0lPMjgNCj4gPiBQ QURfQ1RSTF9QVV8yMmsNCj4gPiArCQkJPjsNCj4gPiArCQl9Ow0KPiA+ICsJCXBpbmN0cmxfcmVz ZXRfbW9jaTogZ3Bpb19yZXNldF9tb2NpIHsNCj4gPiArCQkJZnNsLHBpbnMgPSA8DQo+ID4gKwkJ CQkvKiBSRVNFVF9NT0NJIGNvbnRyb2wgKi8NCj4gPiArCQkJCU1YNlFETF9QQURfRU5FVF9UWF9F Tl9fR1BJTzFfSU8yOA0KPiA+ICsJCQkJCQlQQURfQ1RSTF9QVV8yMmsNCj4gPiArCQkJPjsNCj4g PiArCQl9Ow0KPiA+ICsJCXBpbmN0cmxfdG91Y2hfaW50OiB0b3VjaF9pbnRncnAgew0KPiA+ICsJ CQlmc2wscGlucyA9IDwNCj4gPiArCQkJCS8qIFNUTVBFODExIGludGVycnVwdCAqLw0KPiA+ICsJ CQkJTVg2UURMX1BBRF9LRVlfQ09MMl9fR1BJTzRfSU8xMA0KPiA+IFBBRF9DVFJMX0hZU19QVQ0K PiA+ICsJCQk+Ow0KPiA+ICsJCX07DQo+ID4gKwkJcGluY3RybF91c2RoYzM6IHVzZGhjM2dycCB7 DQo+ID4gKwkJCWZzbCxwaW5zID0gPA0KPiA+ICsJCQkJTVg2UURMX1BBRF9TRDNfQ01EX19TRDNf Q01EwqDCoMKgwqAweDENCj4gPiA3MDU5DQo+ID4gKwkJCQlNWDZRRExfUEFEX1NEM19DTEtfX1NE M19DTEvCoMKgwqDCoDB4MQ0KPiA+IDAwNTkNCj4gPiArCQkJCU1YNlFETF9QQURfU0QzX0RBVDBf X1NEM19EQVRBMA0KPiA+IDB4MTcwNTkNCj4gPiArCQkJCU1YNlFETF9QQURfU0QzX0RBVDFfX1NE M19EQVRBMQ0KPiA+IDB4MTcwNTkNCj4gPiArCQkJCU1YNlFETF9QQURfU0QzX0RBVDJfX1NEM19E QVRBMg0KPiA+IDB4MTcwNTkNCj4gPiArCQkJCU1YNlFETF9QQURfU0QzX0RBVDNfX1NEM19EQVRB Mw0KPiA+IDB4MTcwNTkNCj4gPiArCQkJCU1YNlFETF9QQURfU0QzX0RBVDRfX1NEM19EQVRBNA0K PiA+IDB4MTcwNTkNCj4gPiArCQkJCU1YNlFETF9QQURfU0QzX0RBVDVfX1NEM19EQVRBNQ0KPiA+ IDB4MTcwNTkNCj4gPiArCQkJCU1YNlFETF9QQURfU0QzX0RBVDZfX1NEM19EQVRBNg0KPiA+IDB4 MTcwNTkNCj4gPiArCQkJCU1YNlFETF9QQURfU0QzX0RBVDdfX1NEM19EQVRBNw0KPiA+IDB4MTcw NTkNCj4gPiArCQkJPjsNCj4gPiArCQl9Ow0KPiA+ICsJCXBpbmN0cmxfdXNkaGMzXzEwMG1oejog dXNkaGMzZ3JwLTEwMG1oeiB7IC8qDQo+ID4gMTAwTWh6ICovDQo+IA0KPiBJIGRvIG5vdCBoYXZl IGEgc3Ryb25nIG9waW5pb24gb24gY29tbWVudHMsIGJ1dCBpZiB0aGV5IGFyZSBwdXJlDQo+IGR1 cGxpY2F0aW9uIG9mIHdoYXQgaXMgYWxyZWFkeSB0aGVyZSwgSSBraW5kIG9mIHByZWZlciB0byBu b3QgYWRkDQo+IHRoZW0uLi4NCg0KQWdyZWVkLg0KDQo+ID4gKwkJCWZzbCxwaW5zID0gPA0KPiA+ ICsJCQkJTVg2UURMX1BBRF9TRDNfQ01EX19TRDNfQ01EDQo+ID4gMHgxNzBCOQ0KPiA+ICsJCQkJ TVg2UURMX1BBRF9TRDNfQ0xLX19TRDNfQ0xLDQo+ID4gMHgxMDBCOQ0KPiA+ICsJCQkJTVg2UURM X1BBRF9TRDNfREFUMF9fU0QzX0RBVEEwDQo+ID4gMHgxNzBCOQ0KPiA+ICsJCQkJTVg2UURMX1BB RF9TRDNfREFUMV9fU0QzX0RBVEExDQo+ID4gMHgxNzBCOQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9T RDNfREFUMl9fU0QzX0RBVEEyDQo+ID4gMHgxNzBCOQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9TRDNf REFUM19fU0QzX0RBVEEzDQo+ID4gMHgxNzBCOQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9TRDNfREFU NF9fU0QzX0RBVEE0DQo+ID4gMHgxNzBCOQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9TRDNfREFUNV9f U0QzX0RBVEE1DQo+ID4gMHgxNzBCOQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9TRDNfREFUNl9fU0Qz X0RBVEE2DQo+ID4gMHgxNzBCOQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9TRDNfREFUN19fU0QzX0RB VEE3DQo+ID4gMHgxNzBCOQ0KPiA+ICsJCQk+Ow0KPiA+ICsJCX07DQo+ID4gKwkJcGluY3RybF91 c2RoYzNfMjAwbWh6OiB1c2RoYzNncnAtMjAwbWh6IHsgLyoNCj4gPiAyMDBNaHogKi8NCj4gPiAr CQkJZnNsLHBpbnMgPSA8DQo+ID4gKwkJCQlNWDZRRExfUEFEX1NEM19DTURfX1NEM19DTUQNCj4g PiAweDE3MEY5DQo+ID4gKwkJCQlNWDZRRExfUEFEX1NEM19DTEtfX1NEM19DTEsNCj4gPiAweDEw MEY5DQo+ID4gKwkJCQlNWDZRRExfUEFEX1NEM19EQVQwX19TRDNfREFUQTANCj4gPiAweDE3MEY5 DQo+ID4gKwkJCQlNWDZRRExfUEFEX1NEM19EQVQxX19TRDNfREFUQTENCj4gPiAweDE3MEY5DQo+ ID4gKwkJCQlNWDZRRExfUEFEX1NEM19EQVQyX19TRDNfREFUQTINCj4gPiAweDE3MEY5DQo+ID4g KwkJCQlNWDZRRExfUEFEX1NEM19EQVQzX19TRDNfREFUQTMNCj4gPiAweDE3MEY5DQo+ID4gKwkJ CQlNWDZRRExfUEFEX1NEM19EQVQ0X19TRDNfREFUQTQNCj4gPiAweDE3MEY5DQo+ID4gKwkJCQlN WDZRRExfUEFEX1NEM19EQVQ1X19TRDNfREFUQTUNCj4gPiAweDE3MEY5DQo+ID4gKwkJCQlNWDZR RExfUEFEX1NEM19EQVQ2X19TRDNfREFUQTYNCj4gPiAweDE3MEY5DQo+ID4gKwkJCQlNWDZRRExf UEFEX1NEM19EQVQ3X19TRDNfREFUQTcNCj4gPiAweDE3MEY5DQo+ID4gKwkJCT47DQo+ID4gKwkJ fTsNCj4gPiArCX07DQo+ID4gKw0KPiA+ICsJaXB1MSB7DQo+ID4gKwkJcGluY3RybF9pcHUxX2xj ZGlmOiBpcHUxbGNkaWZncnAgew0KPiA+ICsJCQlmc2wscGlucyA9IDwNCj4gPiArCQkJCU1YNlFE TF9QQURfRUlNX0ExNl9fSVBVMV9ESTFfRElTUF8NCj4gPiBDTEsJMHg2MQ0KPiA+ICsJCQkJLyog REUgKi8NCj4gPiArCQkJCU1YNlFETF9QQURfRUlNX0RBMTBfX0lQVTFfREkxX1BJTjENCj4gPiA1 CTB4NjENCj4gPiArCQkJCS8qIEhTeW5jICovDQo+ID4gKwkJCQlNWDZRRExfUEFEX0VJTV9EQTEx X19JUFUxX0RJMV9QSU4wDQo+ID4gMgkweDYxDQo+ID4gKwkJCQkvKiBWU3luYyAqLw0KPiA+ICsJ CQkJTVg2UURMX1BBRF9FSU1fREExMl9fSVBVMV9ESTFfUElOMA0KPiA+IDMJMHg2MQ0KPiA+ICsJ CQkJTVg2UURMX1BBRF9FSU1fREE5X19JUFUxX0RJU1AxX0RBVA0KPiA+IEEwMAkweDYxDQo+ID4g KwkJCQlNWDZRRExfUEFEX0VJTV9EQThfX0lQVTFfRElTUDFfREFUDQo+ID4gQTAxCTB4NjENCj4g PiArCQkJCU1YNlFETF9QQURfRUlNX0RBN19fSVBVMV9ESVNQMV9EQVQNCj4gPiBBMDIJMHg2MQ0K PiA+ICsJCQkJTVg2UURMX1BBRF9FSU1fREE2X19JUFUxX0RJU1AxX0RBVA0KPiA+IEEwMwkweDYx DQo+ID4gKwkJCQlNWDZRRExfUEFEX0VJTV9EQTVfX0lQVTFfRElTUDFfREFUDQo+ID4gQTA0CTB4 NjENCj4gPiArCQkJCU1YNlFETF9QQURfRUlNX0RBNF9fSVBVMV9ESVNQMV9EQVQNCj4gPiBBMDUJ MHg2MQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9FSU1fREEzX19JUFUxX0RJU1AxX0RBVA0KPiA+IEEw NgkweDYxDQo+ID4gKwkJCQlNWDZRRExfUEFEX0VJTV9EQTJfX0lQVTFfRElTUDFfREFUDQo+ID4g QTA3CTB4NjENCj4gPiArCQkJCU1YNlFETF9QQURfRUlNX0RBMV9fSVBVMV9ESVNQMV9EQVQNCj4g PiBBMDgJMHg2MQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9FSU1fREEwX19JUFUxX0RJU1AxX0RBVA0K PiA+IEEwOQkweDYxDQo+ID4gKwkJCQlNWDZRRExfUEFEX0VJTV9FQjFfX0lQVTFfRElTUDFfREFU DQo+ID4gQTEwCTB4NjENCj4gPiArCQkJCU1YNlFETF9QQURfRUlNX0VCMF9fSVBVMV9ESVNQMV9E QVQNCj4gPiBBMTEJMHg2MQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9FSU1fQTE3X19JUFUxX0RJU1Ax X0RBVA0KPiA+IEExMgkweDYxDQo+ID4gKwkJCQlNWDZRRExfUEFEX0VJTV9BMThfX0lQVTFfRElT UDFfREFUDQo+ID4gQTEzCTB4NjENCj4gPiArCQkJCU1YNlFETF9QQURfRUlNX0ExOV9fSVBVMV9E SVNQMV9EQVQNCj4gPiBBMTQJMHg2MQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9FSU1fQTIwX19JUFUx X0RJU1AxX0RBVA0KPiA+IEExNQkweDYxDQo+ID4gKwkJCQlNWDZRRExfUEFEX0VJTV9BMjFfX0lQ VTFfRElTUDFfREFUDQo+ID4gQTE2CTB4NjENCj4gPiArCQkJCU1YNlFETF9QQURfRUlNX0EyMl9f SVBVMV9ESVNQMV9EQVQNCj4gPiBBMTcJMHg2MQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9FSU1fQTIz X19JUFUxX0RJU1AxX0RBVA0KPiA+IEExOAkweDYxDQo+ID4gKwkJCQlNWDZRRExfUEFEX0VJTV9B MjRfX0lQVTFfRElTUDFfREFUDQo+ID4gQTE5CTB4NjENCj4gPiArCQkJCU1YNlFETF9QQURfRUlN X0QzMV9fSVBVMV9ESVNQMV9EQVQNCj4gPiBBMjAJMHg2MQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9F SU1fRDMwX19JUFUxX0RJU1AxX0RBVA0KPiA+IEEyMQkweDYxDQo+ID4gKwkJCQlNWDZRRExfUEFE X0VJTV9EMjZfX0lQVTFfRElTUDFfREFUDQo+ID4gQTIyCTB4NjENCj4gPiArCQkJCU1YNlFETF9Q QURfRUlNX0QyN19fSVBVMV9ESVNQMV9EQVQNCj4gPiBBMjMJMHg2MQ0KPiA+ICsJCQk+Ow0KPiA+ ICsJCX07DQo+ID4gKwkJcGluY3RybF9jYW1fbWNsazogY2FtX21jbGsgew0KPiA+ICsJCQlmc2ws cGlucyA9IDwNCj4gPiArCQkJCS8qIENBTSBzeXNfbWNsayAqLw0KPiA+ICsJCQkJTVg2UURMX1BB RF9OQU5ERl9DUzJfX0NDTV9DTEtPMg0KPiA+IDB4MDBiMA0KPiA+ICsJCQk+Ow0KPiA+ICsJCX07 DQo+ID4gKwkJcGluY3RybF9pcHUxX2NzaTA6IGlwdTFjc2kwZ3JwIHsgLyogcGFyYWxsZWwNCj4g PiBjYW1lcmEgKi8NCj4gPiArCQkJZnNsLHBpbnMgPSA8DQo+ID4gKwkJCQlNWDZRRExfUEFEX0NT STBfREFUMTJfX0lQVTFfQ1NJMF9EDQo+ID4gQVRBMTLCoMKgMHhiMGIxDQo+ID4gKwkJCQlNWDZR RExfUEFEX0NTSTBfREFUMTNfX0lQVTFfQ1NJMF9EDQo+ID4gQVRBMTPCoMKgMHhiMGIxDQo+ID4g KwkJCQlNWDZRRExfUEFEX0NTSTBfREFUMTRfX0lQVTFfQ1NJMF9EDQo+ID4gQVRBMTTCoMKgMHhi MGIxDQo+ID4gKwkJCQlNWDZRRExfUEFEX0NTSTBfREFUMTVfX0lQVTFfQ1NJMF9EDQo+ID4gQVRB MTXCoMKgMHhiMGIxDQo+ID4gKwkJCQlNWDZRRExfUEFEX0NTSTBfREFUMTZfX0lQVTFfQ1NJMF9E DQo+ID4gQVRBMTbCoMKgMHhiMGIxDQo+ID4gKwkJCQlNWDZRRExfUEFEX0NTSTBfREFUMTdfX0lQ VTFfQ1NJMF9EDQo+ID4gQVRBMTfCoMKgMHhiMGIxDQo+ID4gKwkJCQlNWDZRRExfUEFEX0NTSTBf REFUMThfX0lQVTFfQ1NJMF9EDQo+ID4gQVRBMTjCoMKgMHhiMGIxDQo+ID4gKwkJCQlNWDZRRExf UEFEX0NTSTBfREFUMTlfX0lQVTFfQ1NJMF9EDQo+ID4gQVRBMTnCoMKgMHhiMGIxDQo+ID4gKwkJ CQlNWDZRRExfUEFEX0NTSTBfUElYQ0xLX19JUFUxX0NTSTBfDQo+ID4gUElYQ0xLIDB4YjBiMQ0K PiA+ICsJCQkJTVg2UURMX1BBRF9DU0kwX01DTEtfX0lQVTFfQ1NJMF9IUw0KPiA+IFlOQ8KgwqDC oMKgMHhiMGIxDQo+ID4gKwkJCQlNWDZRRExfUEFEX0NTSTBfVlNZTkNfX0lQVTFfQ1NJMF9WDQo+ ID4gU1lOQ8KgwqDCoDB4YjBiMQ0KPiA+ICsJCQk+Ow0KPiA+ICsJCX07DQo+ID4gKwl9Ow0KPiA+ ICsNCj4gPiArCXB3bSB7DQo+ID4gKwkJcGluY3RybF9wd20xOiBwd20xZ3JwIHsNCj4gPiArCQkJ ZnNsLHBpbnMgPSA8DQo+ID4gKwkJCQlNWDZRRExfUEFEX0dQSU9fOV9fUFdNMV9PVVQNCj4gPiAw eDFiMGIxDQo+ID4gKwkJCT47DQo+ID4gKwkJfTsNCj4gPiArCQlwaW5jdHJsX3B3bTI6IHB3bTJn cnAgew0KPiA+ICsJCQlmc2wscGlucyA9IDwNCj4gPiArCQkJCU1YNlFETF9QQURfR1BJT18xX19Q V00yX09VVA0KPiA+IDB4MWIwYjENCj4gPiArCQkJPjsNCj4gPiArCQl9Ow0KPiA+ICsJCXBpbmN0 cmxfcHdtMzogcHdtM2dycCB7DQo+ID4gKwkJCWZzbCxwaW5zID0gPA0KPiA+ICsJCQkJTVg2UURM X1BBRF9TRDRfREFUMV9fUFdNM19PVVQNCj4gPiAweDFiMGIxDQo+ID4gKwkJCT47DQo+ID4gKwkJ fTsNCj4gPiArCQlwaW5jdHJsX3B3bTQ6IHB3bTRncnAgew0KPiA+ICsJCQlmc2wscGlucyA9IDwN Cj4gPiArCQkJCU1YNlFETF9QQURfU0Q0X0RBVDJfX1BXTTRfT1VUDQo+ID4gMHgxYjBiMQ0KPiA+ ICsJCQk+Ow0KPiA+ICsJCX07DQo+ID4gKwl9Ow0KPiA+ICsNCj4gPiArCXNwZGlmIHsNCj4gPiAr CQlwaW5jdHJsX3NwZGlmOiBzcGRpZmdycCB7DQo+ID4gKwkJCWZzbCxwaW5zID0gPA0KPiA+ICsJ CQkJTVg2UURMX1BBRF9HUElPXzE2X19TUERJRl9JTsKgwqAweDFiDQo+ID4gMGIwDQo+ID4gKwkJ CQlNWDZRRExfUEFEX0dQSU9fMTdfX1NQRElGX09VVA0KPiA+IDB4MWIwYjANCj4gPiArCQkJPjsN Cj4gPiArCQl9Ow0KPiA+ICsJfTsNCj4gPiArDQo+ID4gKwl1YXJ0MSB7DQo+ID4gKwkJcGluY3Ry bF91YXJ0MV9kY2U6IHVhcnQxLWRjZWdycCB7DQo+ID4gKwkJCWZzbCxwaW5zID0gPA0KPiA+ICsJ CQkJTVg2UURMX1BBRF9DU0kwX0RBVDEwX19VQVJUMV9UWF9EQQ0KPiA+IFRBIDB4MWIwYjENCj4g PiArCQkJCU1YNlFETF9QQURfQ1NJMF9EQVQxMV9fVUFSVDFfUlhfREENCj4gPiBUQSAweDFiMGIx DQo+ID4gKwkJCT47DQo+ID4gKwkJfTsNCj4gPiArDQo+ID4gKwkJLyogRFRFIG1vZGUgKi8NCj4g PiArCQlwaW5jdHJsX3VhcnQxX2R0ZTogdWFydDEtZHRlZ3JwIHsNCj4gPiArCQkJZnNsLHBpbnMg PSA8DQo+ID4gKwkJCQlNWDZRRExfUEFEX0NTSTBfREFUMTBfX1VBUlQxX1JYX0RBDQo+ID4gVEEg MHgxYjBiMQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9DU0kwX0RBVDExX19VQVJUMV9UWF9EQQ0KPiA+ IFRBIDB4MWIwYjENCj4gPiArCQkJCU1YNlFETF9QQURfRUlNX0QxOV9fVUFSVDFfUlRTX0INCj4g PiAweDFiMGIxDQo+ID4gKwkJCQlNWDZRRExfUEFEX0VJTV9EMjBfX1VBUlQxX0NUU19CDQo+ID4g MHgxYjBiMQ0KPiA+ICsJCQk+Ow0KPiA+ICsJCX07DQo+ID4gKw0KPiA+ICsJCS8qIEFkZGl0aW9u YWwgRFRSLCBEU1IsIERDRCAqLw0KPiA+ICsJCXBpbmN0cmxfdWFydDFfY3RybDogdWFydDEtY3Ry bGdycCB7DQo+ID4gKwkJCWZzbCxwaW5zID0gPA0KPiA+ICsJCQkJTVg2UURMX1BBRF9FSU1fRDIz X19VQVJUMV9EQ0RfQg0KPiA+IDB4MWIwYjANCj4gPiArCQkJCU1YNlFETF9QQURfRUlNX0QyNF9f VUFSVDFfRFRSX0INCj4gPiAweDFiMGIwDQo+ID4gKwkJCQlNWDZRRExfUEFEX0VJTV9EMjVfX1VB UlQxX0RTUl9CDQo+ID4gMHgxYjBiMA0KPiA+ICsJCQk+Ow0KPiA+ICsJCX07DQo+ID4gKwl9Ow0K PiA+ICsNCj4gPiArCXVhcnQyIHsNCj4gPiArCQlwaW5jdHJsX3VhcnQyX2RjZTogdWFydDItZGNl Z3JwIHsNCj4gPiArCQkJZnNsLHBpbnMgPSA8DQo+ID4gKwkJCQlNWDZRRExfUEFEX1NENF9EQVQ0 X19VQVJUMl9SWF9EQVRBDQo+ID4gCTB4MWIwYjENCj4gPiArCQkJCU1YNlFETF9QQURfU0Q0X0RB VDdfX1VBUlQyX1RYX0RBVEENCj4gPiAJMHgxYjBiMQ0KPiA+ICsJCQk+Ow0KPiA+ICsJCX07DQo+ ID4gKw0KPiA+ICsJCS8qIERURSBtb2RlICovDQo+ID4gKwkJcGluY3RybF91YXJ0Ml9kdGU6IHVh cnQyZ3JwLWR0ZSB7DQo+ID4gKwkJCWZzbCxwaW5zID0gPA0KPiA+ICsJCQkJTVg2UURMX1BBRF9T RDRfREFUNF9fVUFSVDJfVFhfREFUQQ0KPiA+IAkweDFiMGIxDQo+ID4gKwkJCQlNWDZRRExfUEFE X1NENF9EQVQ3X19VQVJUMl9SWF9EQVRBDQo+ID4gCTB4MWIwYjENCj4gPiArCQkJCU1YNlFETF9Q QURfU0Q0X0RBVDZfX1VBUlQyX1JUU19CCQ0KPiA+IDB4MWIwYjENCj4gPiArCQkJCU1YNlFETF9Q QURfU0Q0X0RBVDVfX1VBUlQyX0NUU19CCQ0KPiA+IDB4MWIwYjENCj4gPiArCQkJPjsNCj4gPiAr CQl9Ow0KPiA+ICsJfTsNCj4gPiArDQo+ID4gKwl1YXJ0NCB7DQo+ID4gKwkJcGluY3RybF91YXJ0 NF9kY2U6IHVhcnQ0LWRjZWdycCB7DQo+ID4gKwkJCWZzbCxwaW5zID0gPA0KPiA+ICsJCQkJTVg2 UURMX1BBRF9LRVlfQ09MMF9fVUFSVDRfVFhfREFUQQ0KPiA+IDB4MWIwYjENCj4gPiArCQkJCU1Y NlFETF9QQURfS0VZX1JPVzBfX1VBUlQ0X1JYX0RBVEENCj4gPiAweDFiMGIxDQo+ID4gKwkJCT47 DQo+ID4gKwkJfTsNCj4gPiArDQo+ID4gKwkJLyogRFRFIG1vZGUgKi8NCj4gPiArCQlwaW5jdHJs X3VhcnQ0X2R0ZTogdWFydDQtZHRlZ3JwIHsNCj4gPiArCQkJZnNsLHBpbnMgPSA8DQo+ID4gKwkJ CQlNWDZRRExfUEFEX0tFWV9DT0wwX19VQVJUNF9SWF9EQVRBDQo+ID4gMHgxYjBiMQ0KPiA+ICsJ CQkJTVg2UURMX1BBRF9LRVlfUk9XMF9fVUFSVDRfVFhfREFUQQ0KPiA+IDB4MWIwYjENCj4gPiAr CQkJPjsNCj4gPiArCQl9Ow0KPiA+ICsJfTsNCj4gPiArDQo+ID4gKwl1YXJ0NSB7DQo+ID4gKwkJ cGluY3RybF91YXJ0NV9kY2U6IHVhcnQ1LWRjZWdycCB7DQo+ID4gKwkJCWZzbCxwaW5zID0gPA0K PiA+ICsJCQkJTVg2UURMX1BBRF9LRVlfQ09MMV9fVUFSVDVfVFhfREFUQQ0KPiA+IDB4MWIwYjEN Cj4gPiArCQkJCU1YNlFETF9QQURfS0VZX1JPVzFfX1VBUlQ1X1JYX0RBVEENCj4gPiAweDFiMGIx DQo+ID4gKwkJCT47DQo+ID4gKwkJfTsNCj4gPiArDQo+ID4gKwkJLyogRFRFIG1vZGUgKi8NCj4g PiArCQlwaW5jdHJsX3VhcnQ1X2R0ZTogdWFydDUtZHRlZ3JwIHsNCj4gPiArCQkJZnNsLHBpbnMg PSA8DQo+ID4gKwkJCQlNWDZRRExfUEFEX0tFWV9DT0wxX19VQVJUNV9SWF9EQVRBDQo+ID4gMHgx YjBiMQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9LRVlfUk9XMV9fVUFSVDVfVFhfREFUQQ0KPiA+IDB4 MWIwYjENCj4gPiArCQkJPjsNCj4gPiArCQl9Ow0KPiA+ICsJfTsNCj4gPiArDQo+ID4gKwl1c2Jo IHsNCj4gPiArCQlwaW5jdHJsX3JlZ3VsYXRvcl91c2JoX3B3cjoNCj4gPiBncGlvX3JlZ3VsYXRv cl91c2JoX3B3ciB7DQo+ID4gKwkJCWZzbCxwaW5zID0gPA0KPiA+ICsJCQkJLyogVVNCSF9FTiAq Lw0KPiA+ICsJCQkJTVg2UURMX1BBRF9HUElPXzBfX0dQSU8xX0lPMDANCj4gPiBQQURfQ1RSTF9Q VV8yMmsNCj4gPiArCQkJPjsNCj4gPiArCQl9Ow0KPiA+ICsJfTsNCj4gPiArDQo+ID4gKwl1c2Jv dGcgew0KPiA+ICsJCXBpbmN0cmxfdXNib3RnOiB1c2JvdGdncnAgew0KPiA+ICsJCQlmc2wscGlu cyA9IDwNCj4gPiArCQkJCU1YNlFETF9QQURfRU5FVF9SWF9FUl9fVVNCX09UR19JRA0KPiA+IDB4 MTcwNTkNCj4gPiArCQkJPjsNCj4gPiArCQl9Ow0KPiA+ICsJCXBpbmN0cmxfcmVndWxhdG9yX3Vz Ym90Z19wd3I6DQo+ID4gZ3Bpb19yZWd1bGF0b3JfdXNib3RnX3B3ciB7DQo+ID4gKwkJCWZzbCxw aW5zID0gPA0KPiA+ICsJCQkJLyogVVNCTyBwb3dlciBlbiAqLw0KPiA+ICsJCQkJTVg2UURMX1BB RF9FSU1fRDIyX19HUElPM19JTzIyDQo+ID4gUEFEX0NUUkxfUFVfMjJrDQo+ID4gKwkJCT47DQo+ ID4gKwkJfTsNCj4gPiArCX07DQo+ID4gKw0KPiA+ICsJdXNkaGMgew0KPiA+ICsJCXBpbmN0cmxf bW1jX2NkOiBncGlvX21tY19jZCB7DQo+ID4gKwkJCWZzbCxwaW5zID0gPA0KPiA+ICsJCQkJwqAv KiBNTUMxIENEICovDQo+ID4gKwkJCQlNWDZRRExfUEFEX0RJMF9QSU40X19HUElPNF9JTzIwDQo+ ID4gMHgwMDBiMA0KPiA+ICsJCQk+Ow0KPiA+ICsJCX07DQo+ID4gKwkJcGluY3RybF9zZF9jZDog Z3Bpb19zZF9jZCB7DQo+ID4gKwkJCWZzbCxwaW5zID0gPA0KPiA+ICsJCQkJLyogU0QxIENEICov DQo+ID4gKwkJCQlNWDZRRExfUEFEX05BTkRGX0NTMV9fR1BJTzZfSU8xNA0KPiA+IDB4MDAwYjAN Cj4gPiArCQkJPjsNCj4gPiArCQl9Ow0KPiA+ICsJCXBpbmN0cmxfdXNkaGMxOiB1c2RoYzFncnAg ew0KPiA+ICsJCQlmc2wscGlucyA9IDwNCj4gPiArCQkJCU1YNlFETF9QQURfU0QxX0NNRF9fU0Qx X0NNRMKgwqDCoMKgMHgxDQo+ID4gNzA3MQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9TRDFfQ0xLX19T RDFfQ0xLwqDCoMKgwqAweDENCj4gPiAwMDcxDQo+ID4gKwkJCQlNWDZRRExfUEFEX1NEMV9EQVQw X19TRDFfREFUQTANCj4gPiAweDE3MDcxDQo+ID4gKwkJCQlNWDZRRExfUEFEX1NEMV9EQVQxX19T RDFfREFUQTENCj4gPiAweDE3MDcxDQo+ID4gKwkJCQlNWDZRRExfUEFEX1NEMV9EQVQyX19TRDFf REFUQTINCj4gPiAweDE3MDcxDQo+ID4gKwkJCQlNWDZRRExfUEFEX1NEMV9EQVQzX19TRDFfREFU QTMNCj4gPiAweDE3MDcxDQo+ID4gKwkJCQlNWDZRRExfUEFEX05BTkRGX0QwX19TRDFfREFUQTQN Cj4gPiAweDE3MDcxDQo+ID4gKwkJCQlNWDZRRExfUEFEX05BTkRGX0QxX19TRDFfREFUQTUNCj4g PiAweDE3MDcxDQo+ID4gKwkJCQlNWDZRRExfUEFEX05BTkRGX0QyX19TRDFfREFUQTYNCj4gPiAw eDE3MDcxDQo+ID4gKwkJCQlNWDZRRExfUEFEX05BTkRGX0QzX19TRDFfREFUQTcNCj4gPiAweDE3 MDcxDQo+ID4gKwkJCT47DQo+ID4gKwkJfTsNCj4gPiArCQlwaW5jdHJsX3VzZGhjMjogdXNkaGMy Z3JwIHsNCj4gPiArCQkJZnNsLHBpbnMgPSA8DQo+ID4gKwkJCQlNWDZRRExfUEFEX1NEMl9DTURf X1NEMl9DTUTCoMKgwqDCoDB4MQ0KPiA+IDcwNzENCj4gPiArCQkJCU1YNlFETF9QQURfU0QyX0NM S19fU0QyX0NMS8KgwqDCoMKgMHgxDQo+ID4gMDA3MQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9TRDJf REFUMF9fU0QyX0RBVEEwDQo+ID4gMHgxNzA3MQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9TRDJfREFU MV9fU0QyX0RBVEExDQo+ID4gMHgxNzA3MQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9TRDJfREFUMl9f U0QyX0RBVEEyDQo+ID4gMHgxNzA3MQ0KPiA+ICsJCQkJTVg2UURMX1BBRF9TRDJfREFUM19fU0Qy X0RBVEEzDQo+ID4gMHgxNzA3MQ0KPiA+ICsJCQk+Ow0KPiA+ICsJCX07DQo+ID4gKwl9Ow0KPiA+ ICt9Ow0KPiA+ICsNCj4gPiArJmxkYiB7DQo+ID4gKwlzdGF0dXMgPSAib2theSI7DQo+ID4gK307 DQo+ID4gKw0KPiA+ICsmcHdtMSB7DQo+ID4gKwlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOw0K PiA+ICsJcGluY3RybC0wID0gPCZwaW5jdHJsX3B3bTE+Ow0KPiA+ICsJc3RhdHVzID0gImRpc2Fi bGVkIjsNCj4gPiArfTsNCj4gPiArDQo+ID4gKyZwd20yIHsNCj4gPiArCXBpbmN0cmwtbmFtZXMg PSAiZGVmYXVsdCI7DQo+ID4gKwlwaW5jdHJsLTAgPSA8JnBpbmN0cmxfcHdtMj47DQo+ID4gKwlz dGF0dXMgPSAiZGlzYWJsZWQiOw0KPiA+ICt9Ow0KPiA+ICsNCj4gPiArJnB3bTMgew0KPiA+ICsJ cGluY3RybC1uYW1lcyA9ICJkZWZhdWx0IjsNCj4gPiArCXBpbmN0cmwtMCA9IDwmcGluY3RybF9w d20zPjsNCj4gPiArCXN0YXR1cyA9ICJkaXNhYmxlZCI7DQo+ID4gK307DQo+ID4gKw0KPiA+ICsm cHdtNCB7DQo+ID4gKwlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOw0KPiA+ICsJcGluY3RybC0w ID0gPCZwaW5jdHJsX3B3bTQ+Ow0KPiA+ICsJc3RhdHVzID0gImRpc2FibGVkIjsNCj4gPiArfTsN Cj4gPiArDQo+ID4gKyZzcGRpZiB7DQo+ID4gKwlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOw0K PiA+ICsJcGluY3RybC0wID0gPCZwaW5jdHJsX3NwZGlmPjsNCj4gPiArCXN0YXR1cyA9ICJkaXNh YmxlZCI7DQo+ID4gK307DQo+ID4gKw0KPiA+ICsmc3NpMSB7DQo+ID4gKwlmc2wsbW9kZSA9ICJp MnMtc2xhdmUiOw0KPiA+ICsJc3RhdHVzID0gIm9rYXkiOw0KPiA+ICt9Ow0KPiA+ICsNCj4gPiAr JnVhcnQxIHsNCj4gPiArCXBpbmN0cmwtbmFtZXMgPSAiZGVmYXVsdCI7DQo+ID4gKwlwaW5jdHJs LTAgPSA8JnBpbmN0cmxfdWFydDFfZHRlICZwaW5jdHJsX3VhcnQxX2N0cmw+Ow0KPiA+ICsJZnNs LGR0ZS1tb2RlOw0KPiA+ICsJZnNsLHVhcnQtaGFzLXJ0c2N0czsNCj4gPiArCXN0YXR1cyA9ICJk aXNhYmxlZCI7DQo+ID4gK307DQo+ID4gKw0KPiA+ICsmdWFydDIgew0KPiA+ICsJcGluY3RybC1u YW1lcyA9ICJkZWZhdWx0IjsNCj4gPiArCXBpbmN0cmwtMCA9IDwmcGluY3RybF91YXJ0Ml9kdGU+ Ow0KPiA+ICsJZnNsLGR0ZS1tb2RlOw0KPiA+ICsJZnNsLHVhcnQtaGFzLXJ0c2N0czsNCj4gPiAr CXN0YXR1cyA9ICJkaXNhYmxlZCI7DQo+ID4gK307DQo+ID4gKw0KPiA+ICsmdWFydDQgew0KPiA+ ICsJcGluY3RybC1uYW1lcyA9ICJkZWZhdWx0IjsNCj4gPiArCXBpbmN0cmwtMCA9IDwmcGluY3Ry bF91YXJ0NF9kdGU+Ow0KPiA+ICsJZnNsLGR0ZS1tb2RlOw0KPiA+ICsJc3RhdHVzID0gImRpc2Fi bGVkIjsNCj4gPiArfTsNCj4gPiArDQo+ID4gKyZ1YXJ0NSB7DQo+ID4gKwlwaW5jdHJsLW5hbWVz ID0gImRlZmF1bHQiOw0KPiA+ICsJcGluY3RybC0wID0gPCZwaW5jdHJsX3VhcnQ1X2R0ZT47DQo+ ID4gKwlmc2wsZHRlLW1vZGU7DQo+ID4gKwlzdGF0dXMgPSAiZGlzYWJsZWQiOw0KPiA+ICt9Ow0K PiA+ICsNCj4gPiArJnVzYmgxIHsNCj4gPiArCXZidXMtc3VwcGx5ID0gPCZyZWdfdXNiX2hvc3Rf dmJ1cz47DQo+ID4gKwlzdGF0dXMgPSAiZGlzYWJsZWQiOw0KPiA+ICt9Ow0KPiA+ICsNCj4gPiAr JnVzYm90ZyB7DQo+ID4gKwl2YnVzLXN1cHBseSA9IDwmcmVnX3VzYl9vdGdfdmJ1cz47DQo+ID4g KwlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOw0KPiA+ICsJcGluY3RybC0wID0gPCZwaW5jdHJs X3VzYm90Zz47DQo+ID4gKwlkaXNhYmxlLW92ZXItY3VycmVudDsNCj4gPiArCXN0YXR1cyA9ICJk aXNhYmxlZCI7DQo+ID4gK307DQo+ID4gKw0KPiA+ICsvKiBNTUMxICovDQo+ID4gKyZ1c2RoYzEg ew0KPiA+ICsJbGFiZWwgPSAiTU1DMSI7DQo+IA0KPiBUaGlzLi4uDQo+IA0KPiA+ICsJcGluY3Ry bC1uYW1lcyA9ICJkZWZhdWx0IjsNCj4gPiArCXBpbmN0cmwtMCA9IDwmcGluY3RybF91c2RoYzEg JnBpbmN0cmxfbW1jX2NkPjsNCj4gPiArCWNkLWdwaW9zID0gPCZncGlvNCAyMCBHUElPX0FDVElW RV9MT1c+Ow0KPiA+ICsJdm1tYy1zdXBwbHkgPSA8JnJlZ18zcDN2PjsNCj4gPiArCWJ1cy13aWR0 aCA9IDw4PjsNCj4gPiArCXZvbHRhZ2UtcmFuZ2VzID0gPDMzMDAgMzMwMD47DQo+ID4gKwlzdGF0 dXMgPSAiZGlzYWJsZWQiOw0KPiA+ICt9Ow0KPiA+ICsNCj4gPiArLyogU0QxICovDQo+ID4gKyZ1 c2RoYzIgew0KPiA+ICsJbGFiZWwgPSAiU0QxIjsNCj4gDQo+IC4uLmFuZCB0aGlzIHNlZW0gbm90 IHRvIGJlIHNwZWNpZmllZCB1cHN0cmVhbT8gKGF0IGxlYXN0IG5vdCBpbg0KPiBEb2N1bWVudGF0 aW9uL2RldmljZXRyZWUvYmluZGluZ3MvbW1jL21tYy50eHQ/KQ0KPiBOb3Qgc3VyZSBhYm91dCB0 aGlzLi4uIE9yIGlzIGxhYmVsIGEgY29tbW9uIGNvbnZlbnRpb24gYW5kIGhlbmNlDQo+IGF2YWls YWJsZSBmb3IgYWxsIG5vZGVzPw0KDQpZZXMsIEkgZ3Vlc3Mgb25lIGNhbiBwdXQgbGFiZWxzIGFu eXdoZXJlIGJ1dCBJIGFsc28gZG9uJ3Qgc2VlIHdoYXQgdGhlDQpleGFjdCBwdXJwb3NlIG9mIHRo ZW0gc2hvdWxkIGJlIGluIHRoaXMgY2FzZSBzbyBJIHdpbGwgZHJvcCB0aGVtLg0KDQo+ID4gKwlw aW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOw0KPiA+ICsJcGluY3RybC0wID0gPCZwaW5jdHJsX3Vz ZGhjMiAmcGluY3RybF9zZF9jZD47DQo+ID4gKwljZC1ncGlvcyA9IDwmZ3BpbzYgMTQgR1BJT19B Q1RJVkVfTE9XPjsNCj4gPiArCXZtbWMtc3VwcGx5ID0gPCZyZWdfM3Azdj47DQo+ID4gKwlidXMt d2lkdGggPSA8ND47DQo+ID4gKwl2b2x0YWdlLXJhbmdlcyA9IDwzMzAwIDMzMDA+Ow0KPiA+ICsJ c3RhdHVzID0gImRpc2FibGVkIjsNCj4gPiArfTsNCj4gPiArDQo+ID4gKy8qIGVNTUMgKi8NCj4g PiArJnVzZGhjMyB7DQo+ID4gKwlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOw0KPiA+ICsJcGlu Y3RybC0wID0gPCZwaW5jdHJsX3VzZGhjMz47DQo+ID4gKwl2bW1jLXN1cHBseSA9IDwmcmVnXzNw M3Y+Ow0KPiA+ICsJYnVzLXdpZHRoID0gPDg+Ow0KPiA+ICsJdm9sdGFnZS1yYW5nZXMgPSA8MzMw MCAzMzAwPjsNCj4gPiArCW5vbi1yZW1vdmFibGU7DQo+ID4gKwlzdGF0dXMgPSAib2theSI7DQo+ ID4gK307DQo+ID4gKw0KPiA+ICsmd2VpbSB7DQo+ID4gKwlzdGF0dXMgPSAiZGlzYWJsZWQiOyAv KiB3ZWltIHNpZ25hbHMgbm90IGFjY2Vzc2libGUgb24NCj4gPiBpLk1YNiAqLw0KPiANCj4gVGhl eSBhcmUgYWNjZXNzaWJsZSBvbiB0aGUgaS5NWDYgU29DLi4gYnV0IG1heWJlICJvbiBBcGFsaXMg aU1YNlEvRCIuDQo+IE9yDQo+IGp1c3QgcmVtb3ZlIHRoZSBjb21tZW50LCBzaW5jZSB0aGF0IGlz IGtpbmQgb2Ygd2hhdCBkaXNhYmxlZCBzYXlzPw0KDQpZZXMsIHRoYXQgY29tbWVudCBzZWVtcyBi b2d1cyBhbmQgd2lsbCBiZSBkcm9wcGVkLg0KDQo+ID4gK307DQo+IA0KPiBPdGhlcndpc2U6DQo+ IFJldmlld2VkLWJ5OiBTdGVmYW4gQWduZXIgPHN0ZWZhbkBhZ25lci5jaD4NCg0KVGhhbmtzIQ0K DQo+IC0tDQo+IFN0ZWZhbg0KDQpDaGVlcnMNCg0KTWFyY2VsDQpfX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlz dApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJh ZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754273AbcAHIoE (ORCPT ); Fri, 8 Jan 2016 03:44:04 -0500 Received: from mail-db3on0125.outbound.protection.outlook.com ([157.55.234.125]:38216 "EHLO emea01-db3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751814AbcAHIn7 (ORCPT ); Fri, 8 Jan 2016 03:43:59 -0500 From: Marcel Ziswiler To: "stefan@agner.ch" CC: "linux-kernel@vger.kernel.org" , "shawn.guo@linaro.org" , "robh+dt@kernel.org" , "pawel.moll@arm.com" , "devicetree@vger.kernel.org" , "festevam@gmail.com" , "mark.rutland@arm.com" , "galak@codeaurora.org" , "ijc+devicetree@hellion.org.uk" , "stillcompiling@gmail.com" , "ynezz@true.cz" , "linux-arm-kernel@lists.infradead.org" , "shawnguo@kernel.org" , "l.stach@pengutronix.de" , "kernel@pengutronix.de" , "linux@arm.linux.org.uk" Subject: Re: [PATCH v2 1/2] ARM: dts: imx6: Add support for Toradex Apalis iMX6Q/D SoM Thread-Topic: [PATCH v2 1/2] ARM: dts: imx6: Add support for Toradex Apalis iMX6Q/D SoM Thread-Index: AQHRR9e9Aq7Qay0HnUiIq1vMp55Hg57vmduAgAGzroA= Date: Fri, 8 Jan 2016 08:28:58 +0000 Message-ID: <1452241735.3357.11.camel@toradex.com> References: <1452011942-11940-1-git-send-email-marcel.ziswiler@toradex.com> <1452011942-11940-2-git-send-email-marcel.ziswiler@toradex.com> <7e21f1c5e2e30fb2c7bfd9d47ba6e9d9@agner.ch> In-Reply-To: <7e21f1c5e2e30fb2c7bfd9d47ba6e9d9@agner.ch> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=marcel.ziswiler@toradex.com; x-originating-ip: [84.227.37.153] x-microsoft-exchange-diagnostics: 1;VI1PR05MB0973;5:+nKkzt+EpbHP4qBuqGvf82IVhGBKT/lTaW5m2+Wfa8BOJFG7JOUCmkhqg9j54IP8glyEYTNGE0om3M9gOPJDtHVZ5llhRMer/4tQWcK9+zMTZemtrnhr8Bfal1vu4pp2jQjJY6S2EpogpXT2/x0ztg==;24:zkPNwxyTo3sIQ31tZJA1Y8LvlBKvV8Q76YknqdfX9HU4p246LbskzDk9wxBY23FmWaLadt8pDKsAFrfWha6swywGu6a9ixPqH7rqdemUqk4= x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:VI1PR05MB0973; x-ms-office365-filtering-correlation-id: 9dae1cd7-8245-4924-730b-08d31805c1c9 x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(90676262408878); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(601004)(2401047)(5005006)(8121501046)(520078)(10201501046)(3002001);SRVR:VI1PR05MB0973;BCL:0;PCL:0;RULEID:;SRVR:VI1PR05MB0973; x-forefront-prvs: 0815F8251E x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(6009001)(24454002)(199003)(377424004)(189002)(5250100002)(11100500001)(5004730100002)(86362001)(103116003)(66066001)(19580395003)(1220700001)(6116002)(1730700002)(586003)(87936001)(3846002)(101416001)(19580405001)(575784001)(2501003)(1096002)(106356001)(5008740100001)(106116001)(102836003)(2351001)(33646002)(105586002)(2950100001)(4326007)(2906002)(40100003)(97736004)(2900100001)(54356999)(81156007)(110136002)(5001960100002)(189998001)(76176999)(50986999)(5002640100001)(92566002)(36756003)(32563001)(2004002)(579004)(559001)(569005);DIR:OUT;SFP:1102;SCL:1;SRVR:VI1PR05MB0973;H:VI1PR05MB0974.eurprd05.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;A:1;MX:1;LANG:en; spamdiagnosticoutput: 1:23 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" Content-ID: <285581404C98994FBABA1C8D045EA4DB@eurprd05.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: toradex.com X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Jan 2016 08:28:58.8386 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d9995866-0d9b-4251-8315-093f062abab4 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR05MB0973 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id u088iBKP016041 Hi Stefan On Wed, 2016-01-06 at 22:29 -0800, Stefan Agner wrote: > Hi Marcel, > > On 2016-01-05 08:39, Marcel Ziswiler wrote: > > From: Petr Štetiar > > > > Signed-off-by: Petr Štetiar > > Signed-off-by: Marcel Ziswiler > > --- > > > > Changes in v2: > > - clarify exact Apalis iMX6Q/D SoM type in cover letter > > - clarify exact Apalis iMX6Q/D module type and Ixora carrier board > > in model > >   node > > - got rid of obsolete mmc aliases > > - working SGTL5000 audio/sound integration > > - working STMPE811 touch screen controller integration > > - integrated review feedback from Lucas > > - left and even added some more comments as I don't see why putting > > any > >   explanatory comments in dts' should be such a bad thing to do > > - completely got rid of the memory node as that is something > > typically filled > >   in by the boot loader e.g. U-Boot > > - without the regulators simple-bus it no longer boots > > - even though we supposedly shipped a few hundred V1.0a modules > > drop DCE UART > >   support for now and simplify file layout > > - replaced obsolete no-1-8-v by mainline supported voltage-ranges = > > <3300 3300> > >   usdhc property and yes card detects are indeed active low (;-p) > > - integrated review feedback from Stefan > > - fixed Ethernet PHY reset & interrupt (requires Micrel PHY driver > > to be > >   enabled) > > - fixed HDMI DDC (requires GPIO-based bitbanging I2C to be enabled) > > - fixed SPDIF > > > >  arch/arm/boot/dts/imx6qdl-apalis.dtsi | 1040 > > +++++++++++++++++++++++++++++++++ > >  1 file changed, 1040 insertions(+) > >  create mode 100644 arch/arm/boot/dts/imx6qdl-apalis.dtsi > > > > diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi > > b/arch/arm/boot/dts/imx6qdl-apalis.dtsi > > new file mode 100644 > > index 0000000..6104e2e > > --- /dev/null > > +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi > > @@ -0,0 +1,1040 @@ > > +/* > > + * Copyright 2014-2016 Toradex AG > > + * Copyright 2012 Freescale Semiconductor, Inc. > > + * Copyright 2011 Linaro Ltd. > > + * > > + * This file is dual-licensed: you can use it either under the > > terms > > + * of the GPL or the X11 license, at your option. Note that this > > dual > > + * licensing only applies to this file, and not this project as a > > + * whole. > > + * > > + *  a) This file is free software; you can redistribute it and/or > > + *     modify it under the terms of the GNU General Public License > > + *     version 2 as published by the Free Software Foundation. > > + * > > + *     This file is distributed in the hope that it will be useful > > + *     but WITHOUT ANY WARRANTY; without even the implied warranty > > of > > + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See > > the > > + *     GNU General Public License for more details. > > + * > > + * Or, alternatively > > + * > > + *  b) Permission is hereby granted, free of charge, to any person > > + *     obtaining a copy of this software and associated > > documentation > > + *     files (the "Software"), to deal in the Software without > > + *     restriction, including without limitation the rights to use > > + *     copy, modify, merge, publish, distribute, sublicense, > > and/or > > + *     sell copies of the Software, and to permit persons to whom > > the > > + *     Software is furnished to do so, subject to the following > > + *     conditions: > > + * > > + *     The above copyright notice and this permission notice shall > > be > > + *     included in all copies or substantial portions of the > > Software. > > + * > > + *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND > > + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE > > WARRANTIES > > + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > > + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > > + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY > > + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > > ARISING > > + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE > > OR > > + *     OTHER DEALINGS IN THE SOFTWARE. > > + */ > > + > > +#include > > + > > +/ { > > + model = "Toradex Apalis iMX6Q/D Module"; > > + compatible = "toradex,apalis_imx6q", "fsl,imx6q"; > > + > > + backlight: backlight { > > + compatible = "pwm-backlight"; > > + pwms = <&pwm4 0 5000000>; > > + status = "disabled"; > > + }; > > + > > + /* DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 */ > > + i2cddc: i2c@0 { > > + compatible = "i2c-gpio"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_i2c_ddc>; > > + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH /* sda */ > > +  &gpio2 30 GPIO_ACTIVE_HIGH /* scl */ > > + >; > > + i2c-gpio,delay-us = <2>; /* ~100 kHz */ > > + status = "okay"; > > + }; > > + > > + regulators { > > + compatible = "simple-bus"; > > + > > + reg_1p8v: 1p8v { > > + compatible = "regulator-fixed"; > > + regulator-name = "1P8V"; > > + regulator-min-microvolt = <1800000>; > > + regulator-max-microvolt = <1800000>; > > + regulator-always-on; > > + }; > > + > > + reg_2p5v: 2p5v { > > + compatible = "regulator-fixed"; > > + regulator-name = "2P5V"; > > + regulator-min-microvolt = <2500000>; > > + regulator-max-microvolt = <2500000>; > > + regulator-always-on; > > + }; > > + > > + reg_3p3v: 3p3v { > > + compatible = "regulator-fixed"; > > + regulator-name = "3P3V"; > > + regulator-min-microvolt = <3300000>; > > + regulator-max-microvolt = <3300000>; > > + regulator-always-on; > > + }; > > + > > + reg_usb_otg_vbus: usb_otg_vbus { > > + compatible = "regulator-fixed"; > > + pinctrl-names = "default"; > > + pinctrl-0 = > > <&pinctrl_regulator_usbotg_pwr>; > > + regulator-name = "usb_otg_vbus"; > > + regulator-min-microvolt = <5000000>; > > + regulator-max-microvolt = <5000000>; > > + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; > > + enable-active-high; > > + status = "disabled"; > > + }; > > + > > + /* on module usb hub */ > > + reg_usb_host_vbus_hub: usb_host_vbus_hub { > > + compatible = "regulator-fixed"; > > + pinctrl-names = "default"; > > + pinctrl-0 = > > <&pinctrl_regulator_usbhub_pwr>; > > + regulator-name = "usb_host_vbus_hub"; > > + regulator-min-microvolt = <5000000>; > > + regulator-max-microvolt = <5000000>; > > + gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; > > + startup-delay-us = <2000>; > > + enable-active-high; > > + status = "okay"; > > + }; > > + > > + reg_usb_host_vbus: usb_host_vbus { > > + compatible = "regulator-fixed"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; > > + regulator-name = "usb_host_vbus"; > > + regulator-min-microvolt = <5000000>; > > + regulator-max-microvolt = <5000000>; > > + gpio =  <&gpio1 0 GPIO_ACTIVE_HIGH>; > > + enable-active-high; > > + vin-supply = <®_usb_host_vbus_hub>; > > + status = "disabled"; > > + }; > > + }; > > + > > + sound { > > + compatible = "fsl,imx-audio-sgtl5000"; > > + model = "imx6q-apalis-sgtl5000"; > > + ssi-controller = <&ssi1>; > > + audio-codec = <&codec>; > > + audio-routing = > > + "LINE_IN", "Line In Jack", > > + "MIC_IN", "Mic Jack", > > + "Mic Jack", "Mic Bias", > > + "Headphone Jack", "HP_OUT"; > > + mux-int-port = <1>; > > + mux-ext-port = <4>; > > + }; > > + > > + sound_spdif: sound-spdif { > > + compatible = "fsl,imx-audio-spdif"; > > + model = "imx-spdif"; > > + spdif-controller = <&spdif>; > > + spdif-in; > > + spdif-out; > > + status = "disabled"; > > + }; > > +}; > > + > > +&audmux { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_audmux &pinctrl_audmux_mclk>; > > + status = "okay"; > > +}; > > + > > +/* Apalis SPI1 */ > > +&ecspi1 { > > + fsl,spi-num-chipselects = <1>; > > + cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_spi_cs1>; > > + status = "disabled"; > > +}; > > + > > +/* Apalis SPI2 */ > > +&ecspi2 { > > + fsl,spi-num-chipselects = <1>; > > + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_spi_cs2>; > > + status = "disabled"; > > +}; > > + > > +&fec { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_enet &pinctrl_enet_ctrl>; > > + phy-mode = "rgmii"; > > + phy-handle = <ðphy>; > > + phy-reset-duration = <10>; > > + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; > > + status = "okay"; > > + > > + mdio { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + ethphy: ethernet-phy@7 { > > + interrupt-parent = <&gpio1>; > > + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; > > + reg = <7>; > > + }; > > + }; > > +}; > > + > > +&can1 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_flexcan1>; > > + status = "disabled"; > > +}; > > + > > +&can2 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_flexcan2>; > > + status = "disabled"; > > +}; > > + > > +&hdmi { > > + ddc-i2c-bus = <&i2cddc>; > > + status = "okay"; > > +}; > > + > > +/* > > + * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier > > + * board) > > + */ > > +&i2c1 { > > + clock-frequency = <100000>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_i2c1>; > > + status = "disabled"; > > +}; > > + > > +&i2c2 { > > + clock-frequency = <100000>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_i2c2>; > > + status = "okay"; > > + > > + pmic: pfuze100@08 { > > + compatible = "fsl,pfuze100"; > > + reg = <0x08>; > > + > > + regulators { > > + sw1a_reg: sw1ab { > > + regulator-min-microvolt = > > <300000>; > > + regulator-max-microvolt = > > <1875000>; > > + regulator-boot-on; > > + regulator-always-on; > > + regulator-ramp-delay = <6250>; > > + }; > > + > > + sw1c_reg: sw1c { > > + regulator-min-microvolt = > > <300000>; > > + regulator-max-microvolt = > > <1875000>; > > + regulator-boot-on; > > + regulator-always-on; > > + regulator-ramp-delay = <6250>; > > + }; > > + > > + sw3a_reg: sw3a { > > + regulator-min-microvolt = > > <400000>; > > + regulator-max-microvolt = > > <1975000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + swbst_reg: swbst { > > + regulator-min-microvolt = > > <5000000>; > > + regulator-max-microvolt = > > <5150000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + snvs_reg: vsnvs { > > + regulator-min-microvolt = > > <1000000>; > > + regulator-max-microvolt = > > <3000000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + vref_reg: vrefddr { > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + vgen1_reg: vgen1 { > > + regulator-min-microvolt = > > <800000>; > > + regulator-max-microvolt = > > <1550000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + vgen2_reg: vgen2 { > > + regulator-min-microvolt = > > <800000>; > > + regulator-max-microvolt = > > <1550000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + vgen3_reg: vgen3 { > > + regulator-min-microvolt = > > <1800000>; > > + regulator-max-microvolt = > > <3300000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + vgen4_reg: vgen4 { > > + regulator-min-microvolt = > > <1800000>; > > + regulator-max-microvolt = > > <3300000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + vgen5_reg: vgen5 { > > + regulator-min-microvolt = > > <1800000>; > > + regulator-max-microvolt = > > <3300000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + vgen6_reg: vgen6 { > > + regulator-min-microvolt = > > <1800000>; > > + regulator-max-microvolt = > > <3300000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + }; > > + }; > > + > > + codec: sgtl5000@0a { > > + compatible = "fsl,sgtl5000"; > > + reg = <0x0a>; > > + clocks = <&clks 201>; > > + VDDA-supply = <®_2p5v>; > > + VDDIO-supply = <®_3p3v>; > > Nit: The device tree bindings mention two more properties as required > properties: > micbias-resistor-k-ohms > micbias-voltage-m-volts > > However, both have "If this node is not mentioned", hence I guess > they > are actually optional, but maybe we want to set an explicit value > here? Remember we don't make use of any of that microphone bias stuff on any of our Apalis hardware. > > + }; > > + > > + /* STMPE811 touch screen controller */ > > + stmpe811@41 { > > + compatible = "st,stmpe811"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_touch_int>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + reg = <0x41>; > > + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; > > + interrupt-parent = <&gpio4>; > > + interrupt-controller; > > + id = <0>; > > + blocks = <0x5>; > > + irq-trigger = <0x1>; > > + stmpe_touchscreen { > > + compatible = "st,stmpe-ts"; > > + reg = <0>; > > + /* 3.25 MHz ADC clock speed */ > > + st,adc-freq = <1>; > > + /* 8 sample average control */ > > + st,ave-ctrl = <3>; > > + /* 7 length fractional part in z */ > > + st,fraction-z = <7>; > > + /* > > +  * 50 mA typical 80 mA max touchscreen > > drivers > > +  * current limit value > > +  */ > > + st,i-drive = <1>; > > + /* 12-bit ADC */ > > + st,mod-12b = <1>; > > + /* internal ADC reference */ > > + st,ref-sel = <0>; > > + /* ADC converstion time: 80 clocks */ > > + st,sample-time = <4>; > > + /* 1 ms panel driver settling time */ > > + st,settling = <3>; > > + /* 5 ms touch detect interrupt delay */ > > + st,touch-det-delay = <5>; > > + }; > > + }; > > +}; > > + > > +/* > > + * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 201/203 (unused) > > + */ > > +&i2c3 { > > + clock-frequency = <100000>; > > + pinctrl-names = "default", "recovery"; > > + pinctrl-0 = <&pinctrl_i2c3>; > > + pinctrl-1 = <&pinctrl_i2c3_recovery>; > > + scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; > > + sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; > > + status = "disabled"; > > +}; > > + > > +/* PAD Ctrl values for common settings */ > > +/* > > + * (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | PAD_CTL_PKE > > | > > + *  PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) > > + */ > > +#define PAD_CTRL_HYS_PU 0x1b0b0 > > + > > +/* > > + * (PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | > > + *  PAD_CTL_DSE_40ohm) > > + */ > > +#define PAD_CTRL_HYS_PD 0x130b0 > > + > > +/* > > + * (PAD_CTL_PUS_22K_UP | PAD_CTL_PUE | PAD_CTL_PKE | > > PAD_CTL_SPEED_LOW | > > + *  PAD_CTL_DSE_80ohm) > > + */ > > +#define PAD_CTRL_PU_22k 0x0f058 > > + > > +&iomuxc { > > I think it is a convention to move iomuxc at the very end for better > readability of the rest. At least the Vybrid dts and the more > recently > added imx7d-sdb.dts follow this rule. Yes, while the Tegras have it at the beginning NXP wants it at the end (;-p). > > + ecspi { > > + pinctrl_ecspi1: ecspi1grp { > > + fsl,pins = < > > + MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO > > 0x100b1 > > + MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI > > 0x100b1 > > + MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK > > 0x100b1 > > + >; > > + }; > > + pinctrl_ecspi2: ecspi2grp { > > + fsl,pins = < > > + MX6QDL_PAD_EIM_OE__ECSPI2_MISO > > 0x100b1 > > + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI > > 0x100b1 > > + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK > > 0x100b1 > > + >; > > + }; > > + pinctrl_spi_cs1: spi_cs1 { > > + fsl,pins = < > > + /* SPI1 cs */ > > + MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 > > 0x000b1 > > + >; > > + }; > > + pinctrl_spi_cs2: spi_cs2 { > > + fsl,pins = < > > + /* SPI2 cs */ > > + MX6QDL_PAD_EIM_RW__GPIO2_IO26 > > 0x000b1 > > + >; > > + }; > > + }; > > + > > + flexcan { > > + pinctrl_flexcan1: flexcan1grp { > > + fsl,pins = < > > + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX > > 0x1b0b0 > > + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX > > 0x1b0b0 > > + >; > > + }; > > + pinctrl_flexcan2: flexcan2grp { > > + fsl,pins = < > > + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX > > 0x1b0b0 > > + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX > > 0x1b0b0 > > + >; > > + }; > > + }; > > + > > + gpio { > > + pinctrl_apalis_gpio1: apalis_gpio1 { > > + fsl,pins = < > > + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 > > PAD_CTRL_HYS_PD > > + >; > > + }; > > + pinctrl_apalis_gpio2: apalis_gpio2 { > > + fsl,pins = < > > + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 > > PAD_CTRL_HYS_PD > > + >; > > + }; > > + pinctrl_apalis_gpio3: apalis_gpio3 { > > + fsl,pins = < > > + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 > > PAD_CTRL_HYS_PD > > + >; > > + }; > > + pinctrl_apalis_gpio4: apalis_gpio4 { > > + fsl,pins = < > > + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 > > PAD_CTRL_HYS_PD > > + >; > > + }; > > + pinctrl_apalis_gpio5: apalis_gpio5 { > > + fsl,pins = < > > + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 > > PAD_CTRL_HYS_PD > > + >; > > + }; > > + pinctrl_apalis_gpio6: apalis_gpio6 { > > + fsl,pins = < > > + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 > > + PAD_CTRL_HYS_PD > > The 80 character limit normally is not enforced for device trees, > hence > I would remove that line break here... Yes, and then trying to teach patman to actually ignore that warning (;-p). > > + >; > > + }; > > + pinctrl_apalis_gpio7: apalis_gpio7 { > > + fsl,pins = < > > + MX6QDL_PAD_GPIO_2__GPIO1_IO02 > > PAD_CTRL_HYS_PD > > + >; > > + }; > > + pinctrl_apalis_gpio8: apalis_gpio8 { > > + fsl,pins = < > > + MX6QDL_PAD_GPIO_6__GPIO1_IO06 > > PAD_CTRL_HYS_PD > > + >; > > + }; > > + pinctrl_gpio_keys: gpio_keys { > > + fsl,pins = < > > + /* Power Button */ > > + MX6QDL_PAD_GPIO_4__GPIO1_IO04 > > PAD_CTRL_HYS_PU > > + >; > > + }; > > + }; > > + > > + hdmi { > > + pinctrl_hdmi_cec: hdmicecgrp { > > + fsl,pins = < > > + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_L > > INE 0x1f8b0 > > + >; > > + }; > > + }; > > + > > + i2c { > > + pinctrl_i2c_ddc: i2c_ddc { > > + fsl,pins = < > > + /* DDC bitbang */ > > + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 > > PAD_CTRL_HYS_PU > > + MX6QDL_PAD_EIM_D16__GPIO3_IO16 > > PAD_CTRL_HYS_PU > > + >; > > + }; > > + pinctrl_i2c1: i2c1grp { > > + fsl,pins = < > > + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA > > 0x4001b8b1 > > + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL > > 0x4001b8b1 > > + >; > > + }; > > + pinctrl_i2c3: i2c3grp { > > + fsl,pins = < > > + MX6QDL_PAD_EIM_D17__I2C3_SCL > > 0x4001b8b1 > > + MX6QDL_PAD_EIM_D18__I2C3_SDA > > 0x4001b8b1 > > + >; > > + }; > > + pinctrl_i2c3_recovery: i2c3-recoverygrp { > > + fsl,pins = < > > + MX6QDL_PAD_EIM_D17__GPIO3_IO17 > > 0x4001b8b1 > > + MX6QDL_PAD_EIM_D18__GPIO3_IO18 > > 0x4001b8b1 > > + >; > > + }; > > + }; > > + > > + /* pins used on module */ > > + imx6q-apalis { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_reset_moci > > &pinctrl_emmc_reset>; > > + pinctrl_audmux: audmuxgrp { > > + fsl,pins = < > > + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC > > 0x130b0 > > + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD > > 0x130b0 > > + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS > > 0x130b0 > > + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD > > 0x130b0 > > + >; > > + }; > > + pinctrl_audmux_mclk: audmux_mclk { > > + fsl,pins = < > > + /* SGTL5000 sys_mclk */ > > + MX6QDL_PAD_GPIO_5__CCM_CLKO1 > > 0x130b0 > > + >; > > + }; > > + pinctrl_emmc_reset: emmc_reset { > > + fsl,pins = < > > + /* eMMC reset, leave it alone */ > > + MX6QDL_PAD_SD3_RST__GPIO7_IO08 > > PAD_CTRL_PU_22k > > + >; > > + }; > > + pinctrl_enet: enetgrp { > > + fsl,pins = < > > + MX6QDL_PAD_ENET_MDIO__ENET_MDIO > > 0x100b0 > > + MX6QDL_PAD_ENET_MDC__ENET_MDC > > 0x100b0 > > + MX6QDL_PAD_RGMII_TXC__RGMII_TXC > > 0x100b0 > > + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 > > 0x100b0 > > + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 > > 0x100b0 > > + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 > > 0x100b0 > > + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 > > 0x100b0 > > + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_ > > CTL 0x100b0 > > + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_C > > LK 0x100b0 > > + MX6QDL_PAD_RGMII_RXC__RGMII_RXC > > 0x1b0b0 > > + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 > > 0x1b0b0 > > + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 > > 0x1b0b0 > > + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 > > 0x1b0b0 > > + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 > > 0x1b0b0 > > + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_ > > CTL 0x1b0b0 > > + >; > > + }; > > + pinctrl_enet_ctrl: enet_ctrlgrp { > > + fsl,pins = < > > + /* Ethernet PHY reset */ > > + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 > > 0x000b0 > > + /* Ethernet PHY interrupt */ > > + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 > > 0x000b1 > > + >; > > + }; > > + pinctrl_i2c2: i2c2grp { > > + fsl,pins = < > > + MX6QDL_PAD_KEY_COL3__I2C2_SCL > > 0x4001b8b1 > > + MX6QDL_PAD_KEY_ROW3__I2C2_SDA > > 0x4001b8b1 > > + >; > > + }; > > + pinctrl_ipu2_vdac: ipu2vdacgrp { > > + fsl,pins = < > > + MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_ > > DISP_CLK 0xd1 > > + MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN > > 15       0xd1 > > + MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN0 > > 2        0xd1 > > + MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN0 > > 3        0xd1 > > + MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_ > > DATA00   0xf9 > > + MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_ > > DATA01   0xf9 > > + MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_ > > DATA02   0xf9 > > + MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_ > > DATA03   0xf9 > > + MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_ > > DATA04   0xf9 > > + MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_ > > DATA05   0xf9 > > + MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_ > > DATA06   0xf9 > > + MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_ > > DATA07   0xf9 > > + MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_ > > DATA08   0xf9 > > + MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_ > > DATA09   0xf9 > > + MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0 > > _DATA10  0xf9 > > + MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0 > > _DATA11  0xf9 > > + MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0 > > _DATA12  0xf9 > > + MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0 > > _DATA13  0xf9 > > + MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0 > > _DATA14  0xf9 > > + MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0 > > _DATA15  0xf9 > > + >; > > + }; > > + pinctrl_regulator_usbhub_pwr: > > gpio_regulator_usbhub_pwr { > > + fsl,pins = < > > + /* USBH_HUB_EN */ > > + MX6QDL_PAD_EIM_D28__GPIO3_IO28 > > PAD_CTRL_PU_22k > > + >; > > + }; > > + pinctrl_reset_moci: gpio_reset_moci { > > + fsl,pins = < > > + /* RESET_MOCI control */ > > + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 > > + PAD_CTRL_PU_22k > > + >; > > + }; > > + pinctrl_touch_int: touch_intgrp { > > + fsl,pins = < > > + /* STMPE811 interrupt */ > > + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 > > PAD_CTRL_HYS_PU > > + >; > > + }; > > + pinctrl_usdhc3: usdhc3grp { > > + fsl,pins = < > > + MX6QDL_PAD_SD3_CMD__SD3_CMD    0x1 > > 7059 > > + MX6QDL_PAD_SD3_CLK__SD3_CLK    0x1 > > 0059 > > + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 > > 0x17059 > > + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 > > 0x17059 > > + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 > > 0x17059 > > + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 > > 0x17059 > > + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 > > 0x17059 > > + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 > > 0x17059 > > + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 > > 0x17059 > > + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 > > 0x17059 > > + >; > > + }; > > + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { /* > > 100Mhz */ > > I do not have a strong opinion on comments, but if they are pure > duplication of what is already there, I kind of prefer to not add > them... Agreed. > > + fsl,pins = < > > + MX6QDL_PAD_SD3_CMD__SD3_CMD > > 0x170B9 > > + MX6QDL_PAD_SD3_CLK__SD3_CLK > > 0x100B9 > > + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 > > 0x170B9 > > + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 > > 0x170B9 > > + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 > > 0x170B9 > > + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 > > 0x170B9 > > + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 > > 0x170B9 > > + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 > > 0x170B9 > > + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 > > 0x170B9 > > + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 > > 0x170B9 > > + >; > > + }; > > + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { /* > > 200Mhz */ > > + fsl,pins = < > > + MX6QDL_PAD_SD3_CMD__SD3_CMD > > 0x170F9 > > + MX6QDL_PAD_SD3_CLK__SD3_CLK > > 0x100F9 > > + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 > > 0x170F9 > > + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 > > 0x170F9 > > + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 > > 0x170F9 > > + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 > > 0x170F9 > > + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 > > 0x170F9 > > + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 > > 0x170F9 > > + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 > > 0x170F9 > > + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 > > 0x170F9 > > + >; > > + }; > > + }; > > + > > + ipu1 { > > + pinctrl_ipu1_lcdif: ipu1lcdifgrp { > > + fsl,pins = < > > + MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_ > > CLK 0x61 > > + /* DE */ > > + MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN1 > > 5 0x61 > > + /* HSync */ > > + MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN0 > > 2 0x61 > > + /* VSync */ > > + MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN0 > > 3 0x61 > > + MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DAT > > A00 0x61 > > + MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DAT > > A01 0x61 > > + MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DAT > > A02 0x61 > > + MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DAT > > A03 0x61 > > + MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DAT > > A04 0x61 > > + MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DAT > > A05 0x61 > > + MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DAT > > A06 0x61 > > + MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DAT > > A07 0x61 > > + MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DAT > > A08 0x61 > > + MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DAT > > A09 0x61 > > + MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DAT > > A10 0x61 > > + MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DAT > > A11 0x61 > > + MX6QDL_PAD_EIM_A17__IPU1_DISP1_DAT > > A12 0x61 > > + MX6QDL_PAD_EIM_A18__IPU1_DISP1_DAT > > A13 0x61 > > + MX6QDL_PAD_EIM_A19__IPU1_DISP1_DAT > > A14 0x61 > > + MX6QDL_PAD_EIM_A20__IPU1_DISP1_DAT > > A15 0x61 > > + MX6QDL_PAD_EIM_A21__IPU1_DISP1_DAT > > A16 0x61 > > + MX6QDL_PAD_EIM_A22__IPU1_DISP1_DAT > > A17 0x61 > > + MX6QDL_PAD_EIM_A23__IPU1_DISP1_DAT > > A18 0x61 > > + MX6QDL_PAD_EIM_A24__IPU1_DISP1_DAT > > A19 0x61 > > + MX6QDL_PAD_EIM_D31__IPU1_DISP1_DAT > > A20 0x61 > > + MX6QDL_PAD_EIM_D30__IPU1_DISP1_DAT > > A21 0x61 > > + MX6QDL_PAD_EIM_D26__IPU1_DISP1_DAT > > A22 0x61 > > + MX6QDL_PAD_EIM_D27__IPU1_DISP1_DAT > > A23 0x61 > > + >; > > + }; > > + pinctrl_cam_mclk: cam_mclk { > > + fsl,pins = < > > + /* CAM sys_mclk */ > > + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 > > 0x00b0 > > + >; > > + }; > > + pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel > > camera */ > > + fsl,pins = < > > + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_D > > ATA12  0xb0b1 > > + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_D > > ATA13  0xb0b1 > > + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_D > > ATA14  0xb0b1 > > + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_D > > ATA15  0xb0b1 > > + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_D > > ATA16  0xb0b1 > > + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_D > > ATA17  0xb0b1 > > + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_D > > ATA18  0xb0b1 > > + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_D > > ATA19  0xb0b1 > > + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_ > > PIXCLK 0xb0b1 > > + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HS > > YNC    0xb0b1 > > + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_V > > SYNC   0xb0b1 > > + >; > > + }; > > + }; > > + > > + pwm { > > + pinctrl_pwm1: pwm1grp { > > + fsl,pins = < > > + MX6QDL_PAD_GPIO_9__PWM1_OUT > > 0x1b0b1 > > + >; > > + }; > > + pinctrl_pwm2: pwm2grp { > > + fsl,pins = < > > + MX6QDL_PAD_GPIO_1__PWM2_OUT > > 0x1b0b1 > > + >; > > + }; > > + pinctrl_pwm3: pwm3grp { > > + fsl,pins = < > > + MX6QDL_PAD_SD4_DAT1__PWM3_OUT > > 0x1b0b1 > > + >; > > + }; > > + pinctrl_pwm4: pwm4grp { > > + fsl,pins = < > > + MX6QDL_PAD_SD4_DAT2__PWM4_OUT > > 0x1b0b1 > > + >; > > + }; > > + }; > > + > > + spdif { > > + pinctrl_spdif: spdifgrp { > > + fsl,pins = < > > + MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b > > 0b0 > > + MX6QDL_PAD_GPIO_17__SPDIF_OUT > > 0x1b0b0 > > + >; > > + }; > > + }; > > + > > + uart1 { > > + pinctrl_uart1_dce: uart1-dcegrp { > > + fsl,pins = < > > + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DA > > TA 0x1b0b1 > > + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DA > > TA 0x1b0b1 > > + >; > > + }; > > + > > + /* DTE mode */ > > + pinctrl_uart1_dte: uart1-dtegrp { > > + fsl,pins = < > > + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DA > > TA 0x1b0b1 > > + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DA > > TA 0x1b0b1 > > + MX6QDL_PAD_EIM_D19__UART1_RTS_B > > 0x1b0b1 > > + MX6QDL_PAD_EIM_D20__UART1_CTS_B > > 0x1b0b1 > > + >; > > + }; > > + > > + /* Additional DTR, DSR, DCD */ > > + pinctrl_uart1_ctrl: uart1-ctrlgrp { > > + fsl,pins = < > > + MX6QDL_PAD_EIM_D23__UART1_DCD_B > > 0x1b0b0 > > + MX6QDL_PAD_EIM_D24__UART1_DTR_B > > 0x1b0b0 > > + MX6QDL_PAD_EIM_D25__UART1_DSR_B > > 0x1b0b0 > > + >; > > + }; > > + }; > > + > > + uart2 { > > + pinctrl_uart2_dce: uart2-dcegrp { > > + fsl,pins = < > > + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA > > 0x1b0b1 > > + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA > > 0x1b0b1 > > + >; > > + }; > > + > > + /* DTE mode */ > > + pinctrl_uart2_dte: uart2grp-dte { > > + fsl,pins = < > > + MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA > > 0x1b0b1 > > + MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA > > 0x1b0b1 > > + MX6QDL_PAD_SD4_DAT6__UART2_RTS_B > > 0x1b0b1 > > + MX6QDL_PAD_SD4_DAT5__UART2_CTS_B > > 0x1b0b1 > > + >; > > + }; > > + }; > > + > > + uart4 { > > + pinctrl_uart4_dce: uart4-dcegrp { > > + fsl,pins = < > > + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA > > 0x1b0b1 > > + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA > > 0x1b0b1 > > + >; > > + }; > > + > > + /* DTE mode */ > > + pinctrl_uart4_dte: uart4-dtegrp { > > + fsl,pins = < > > + MX6QDL_PAD_KEY_COL0__UART4_RX_DATA > > 0x1b0b1 > > + MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA > > 0x1b0b1 > > + >; > > + }; > > + }; > > + > > + uart5 { > > + pinctrl_uart5_dce: uart5-dcegrp { > > + fsl,pins = < > > + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA > > 0x1b0b1 > > + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA > > 0x1b0b1 > > + >; > > + }; > > + > > + /* DTE mode */ > > + pinctrl_uart5_dte: uart5-dtegrp { > > + fsl,pins = < > > + MX6QDL_PAD_KEY_COL1__UART5_RX_DATA > > 0x1b0b1 > > + MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA > > 0x1b0b1 > > + >; > > + }; > > + }; > > + > > + usbh { > > + pinctrl_regulator_usbh_pwr: > > gpio_regulator_usbh_pwr { > > + fsl,pins = < > > + /* USBH_EN */ > > + MX6QDL_PAD_GPIO_0__GPIO1_IO00 > > PAD_CTRL_PU_22k > > + >; > > + }; > > + }; > > + > > + usbotg { > > + pinctrl_usbotg: usbotggrp { > > + fsl,pins = < > > + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID > > 0x17059 > > + >; > > + }; > > + pinctrl_regulator_usbotg_pwr: > > gpio_regulator_usbotg_pwr { > > + fsl,pins = < > > + /* USBO power en */ > > + MX6QDL_PAD_EIM_D22__GPIO3_IO22 > > PAD_CTRL_PU_22k > > + >; > > + }; > > + }; > > + > > + usdhc { > > + pinctrl_mmc_cd: gpio_mmc_cd { > > + fsl,pins = < > > +  /* MMC1 CD */ > > + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 > > 0x000b0 > > + >; > > + }; > > + pinctrl_sd_cd: gpio_sd_cd { > > + fsl,pins = < > > + /* SD1 CD */ > > + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 > > 0x000b0 > > + >; > > + }; > > + pinctrl_usdhc1: usdhc1grp { > > + fsl,pins = < > > + MX6QDL_PAD_SD1_CMD__SD1_CMD    0x1 > > 7071 > > + MX6QDL_PAD_SD1_CLK__SD1_CLK    0x1 > > 0071 > > + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 > > 0x17071 > > + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 > > 0x17071 > > + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 > > 0x17071 > > + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 > > 0x17071 > > + MX6QDL_PAD_NANDF_D0__SD1_DATA4 > > 0x17071 > > + MX6QDL_PAD_NANDF_D1__SD1_DATA5 > > 0x17071 > > + MX6QDL_PAD_NANDF_D2__SD1_DATA6 > > 0x17071 > > + MX6QDL_PAD_NANDF_D3__SD1_DATA7 > > 0x17071 > > + >; > > + }; > > + pinctrl_usdhc2: usdhc2grp { > > + fsl,pins = < > > + MX6QDL_PAD_SD2_CMD__SD2_CMD    0x1 > > 7071 > > + MX6QDL_PAD_SD2_CLK__SD2_CLK    0x1 > > 0071 > > + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 > > 0x17071 > > + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 > > 0x17071 > > + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 > > 0x17071 > > + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 > > 0x17071 > > + >; > > + }; > > + }; > > +}; > > + > > +&ldb { > > + status = "okay"; > > +}; > > + > > +&pwm1 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_pwm1>; > > + status = "disabled"; > > +}; > > + > > +&pwm2 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_pwm2>; > > + status = "disabled"; > > +}; > > + > > +&pwm3 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_pwm3>; > > + status = "disabled"; > > +}; > > + > > +&pwm4 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_pwm4>; > > + status = "disabled"; > > +}; > > + > > +&spdif { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_spdif>; > > + status = "disabled"; > > +}; > > + > > +&ssi1 { > > + fsl,mode = "i2s-slave"; > > + status = "okay"; > > +}; > > + > > +&uart1 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; > > + fsl,dte-mode; > > + fsl,uart-has-rtscts; > > + status = "disabled"; > > +}; > > + > > +&uart2 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_uart2_dte>; > > + fsl,dte-mode; > > + fsl,uart-has-rtscts; > > + status = "disabled"; > > +}; > > + > > +&uart4 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_uart4_dte>; > > + fsl,dte-mode; > > + status = "disabled"; > > +}; > > + > > +&uart5 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_uart5_dte>; > > + fsl,dte-mode; > > + status = "disabled"; > > +}; > > + > > +&usbh1 { > > + vbus-supply = <®_usb_host_vbus>; > > + status = "disabled"; > > +}; > > + > > +&usbotg { > > + vbus-supply = <®_usb_otg_vbus>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_usbotg>; > > + disable-over-current; > > + status = "disabled"; > > +}; > > + > > +/* MMC1 */ > > +&usdhc1 { > > + label = "MMC1"; > > This... > > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; > > + cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; > > + vmmc-supply = <®_3p3v>; > > + bus-width = <8>; > > + voltage-ranges = <3300 3300>; > > + status = "disabled"; > > +}; > > + > > +/* SD1 */ > > +&usdhc2 { > > + label = "SD1"; > > ...and this seem not to be specified upstream? (at least not in > Documentation/devicetree/bindings/mmc/mmc.txt?) > Not sure about this... Or is label a common convention and hence > available for all nodes? Yes, I guess one can put labels anywhere but I also don't see what the exact purpose of them should be in this case so I will drop them. > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; > > + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; > > + vmmc-supply = <®_3p3v>; > > + bus-width = <4>; > > + voltage-ranges = <3300 3300>; > > + status = "disabled"; > > +}; > > + > > +/* eMMC */ > > +&usdhc3 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_usdhc3>; > > + vmmc-supply = <®_3p3v>; > > + bus-width = <8>; > > + voltage-ranges = <3300 3300>; > > + non-removable; > > + status = "okay"; > > +}; > > + > > +&weim { > > + status = "disabled"; /* weim signals not accessible on > > i.MX6 */ > > They are accessible on the i.MX6 SoC.. but maybe "on Apalis iMX6Q/D". > Or > just remove the comment, since that is kind of what disabled says? Yes, that comment seems bogus and will be dropped. > > +}; > > Otherwise: > Reviewed-by: Stefan Agner Thanks! > -- > Stefan Cheers Marcel