From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758486AbcAMUMx (ORCPT ); Wed, 13 Jan 2016 15:12:53 -0500 Received: from mx1.redhat.com ([209.132.183.28]:41228 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758457AbcAMUMu (ORCPT ); Wed, 13 Jan 2016 15:12:50 -0500 Date: Wed, 13 Jan 2016 22:12:44 +0200 From: "Michael S. Tsirkin" To: linux-kernel@vger.kernel.org, Linus Torvalds Cc: Davidlohr Bueso , Peter Zijlstra , Ingo Molnar , Thomas Gleixner , "Paul E. McKenney" , the arch/x86 maintainers , Davidlohr Bueso , "H. Peter Anvin" , virtualization , Borislav Petkov , Andy Lutomirski , Ingo Molnar , Borislav Petkov , Arnd Bergmann , Andrey Konovalov , Andy Lutomirski Subject: [PATCH v3 4/4] x86: drop mfence in favor of lock+addl Message-ID: <1452715911-12067-5-git-send-email-mst@redhat.com> References: <1452715911-12067-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1452715911-12067-1-git-send-email-mst@redhat.com> X-Mutt-Fcc: =sent Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org mfence appears to be way slower than a locked instruction - let's use lock+add unconditionally, as we always did on old 32-bit. Just poking at SP would be the most natural, but if we then read the value from SP, we get a false dependency which will slow us down. This was noted in this article: http://shipilev.net/blog/2014/on-the-fence-with-dependencies/ And is easy to reproduce by sticking a barrier in a small non-inline function. So let's use a negative offset - which avoids this problem since we build with the red zone disabled. Update rmb/wmb on 32 bit to use the negative offset, too, for consistency. Suggested-by: Andy Lutomirski Signed-off-by: Michael S. Tsirkin --- arch/x86/include/asm/barrier.h | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/barrier.h b/arch/x86/include/asm/barrier.h index bfb28ca..9a2d257 100644 --- a/arch/x86/include/asm/barrier.h +++ b/arch/x86/include/asm/barrier.h @@ -11,16 +11,15 @@ */ #ifdef CONFIG_X86_32 -#define mb() asm volatile(ALTERNATIVE("lock; addl $0,0(%%esp)", "mfence", \ - X86_FEATURE_XMM2) ::: "memory", "cc") -#define rmb() asm volatile(ALTERNATIVE("lock; addl $0,0(%%esp)", "lfence", \ +#define mb() asm volatile("lock; addl $0,-4(%%esp)" ::: "memory", "cc") +#define rmb() asm volatile(ALTERNATIVE("lock; addl $0,-4(%%esp)", "lfence", \ X86_FEATURE_XMM2) ::: "memory", "cc") -#define wmb() asm volatile(ALTERNATIVE("lock; addl $0,0(%%esp)", "sfence", \ +#define wmb() asm volatile(ALTERNATIVE("lock; addl $0,-4(%%esp)", "sfence", \ X86_FEATURE_XMM2) ::: "memory", "cc") #else -#define mb() asm volatile("mfence":::"memory") -#define rmb() asm volatile("lfence":::"memory") -#define wmb() asm volatile("sfence" ::: "memory") +#define mb() asm volatile("lock; addl $0,-4(%%rsp)" ::: "memory", "cc") +#define rmb() asm volatile("lfence" ::: "memory") +#define wmb() asm volatile("sfence" ::: "memory") #endif #ifdef CONFIG_X86_PPRO_FENCE -- MST