From: Imre Deak <imre.deak@intel.com>
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/6] drm/i915: Dump ddi_pll_sel in hex instead of decimal on HSW/BDW
Date: Thu, 18 Feb 2016 15:19:04 +0200 [thread overview]
Message-ID: <1455801544.7638.1.camel@intel.com> (raw)
In-Reply-To: <1455738073-14502-2-git-send-email-ville.syrjala@linux.intel.com>
On ke, 2016-02-17 at 21:41 +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On HSW/BDW ddi_pll_sel is the actual register value. Let's dump
> it in hex so that people migth actually understand what it says.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index afcabe455ad1..f0f88061a9e5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12220,7 +12220,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
> pipe_config->dpll_hw_state.cfgcr1,
> pipe_config->dpll_hw_state.cfgcr2);
> } else if (HAS_DDI(dev)) {
> - DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
> + DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
> pipe_config->ddi_pll_sel,
> pipe_config->dpll_hw_state.wrpll,
> pipe_config->dpll_hw_state.spll);
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next prev parent reply other threads:[~2016-02-18 13:19 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-17 19:41 [PATCH 0/6] drm/i915: Some FDI related dotclock stuff ville.syrjala
2016-02-17 19:41 ` [PATCH 1/6] drm/i915: Dump ddi_pll_sel in hex instead of decimal on HSW/BDW ville.syrjala
2016-02-18 13:19 ` Imre Deak [this message]
2016-02-17 19:41 ` [PATCH 2/6] drm/i915: Move the encoder vs. FDI dotclock check out from encoder .get_config() ville.syrjala
2016-02-18 18:18 ` Imre Deak
2016-02-17 19:41 ` [PATCH 3/6] drm/i915: Remove the SPLL==270Mhz assumption from intel_fdi_link_freq() ville.syrjala
2016-02-18 18:28 ` Imre Deak
2016-02-17 19:41 ` [PATCH 4/6] drm/i915: Make the LPT iclkip 20MHz case more generic ville.syrjala
2016-02-19 13:54 ` Zanoni, Paulo R
2016-02-19 14:04 ` Imre Deak
2016-02-17 19:41 ` [PATCH 5/6] drm/i915: Read out VGA dotclock properly on LPT ville.syrjala
2016-02-19 14:17 ` Imre Deak
2016-02-17 19:41 ` [PATCH 6/6] drm/i915: Try to fix CRT port clock limits ville.syrjala
2016-02-19 14:58 ` Imre Deak
2016-02-19 13:45 ` ✗ Fi.CI.BAT: failure for drm/i915: Some FDI related dotclock stuff Patchwork
2016-02-25 18:15 ` Ville Syrjälä
2016-03-01 11:13 ` [PATCH 0/6] " Ville Syrjälä
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