From mboxrd@z Thu Jan 1 00:00:00 1970 From: andre.przywara@arm.com (Andre Przywara) Date: Mon, 22 Feb 2016 18:20:47 +0000 Subject: [PATCH v3 02/10] ARM: dts: sunxi: make PLL8 in the H3 a proper clock In-Reply-To: <1456165255-31013-1-git-send-email-andre.przywara@arm.com> References: <1456165255-31013-1-git-send-email-andre.przywara@arm.com> Message-ID: <1456165255-31013-3-git-send-email-andre.przywara@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Now that we can reuse the A31 PLL6 clock driver for clocks other then PLL6 itself, describe the PLL8 clock properly. Signed-off-by: Andre Przywara --- arch/arm/boot/dts/sun8i-h3.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 3ba65c2..d84ea9b 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -137,12 +137,12 @@ clock-output-names = "pll6d2"; }; - /* dummy clock until pll6 can be reused */ - pll8: pll8_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1>; - clock-output-names = "pll8"; + pll8: clk at c01c20044 { + #clock-cells = <1>; + compatible = "allwinner,sun6i-a31-pll6-clk"; + reg = <0x01c20044 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll8", "pll8x2"; }; cpu: cpu_clk at 01c20050 { @@ -243,7 +243,7 @@ #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; clock-output-names = "mmc0", "mmc0_output", "mmc0_sample"; @@ -253,7 +253,7 @@ #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; clock-output-names = "mmc1", "mmc1_output", "mmc1_sample"; @@ -263,7 +263,7 @@ #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; clock-output-names = "mmc2", "mmc2_output", "mmc2_sample"; -- 2.6.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andre Przywara Subject: [PATCH v3 02/10] ARM: dts: sunxi: make PLL8 in the H3 a proper clock Date: Mon, 22 Feb 2016 18:20:47 +0000 Message-ID: <1456165255-31013-3-git-send-email-andre.przywara@arm.com> References: <1456165255-31013-1-git-send-email-andre.przywara@arm.com> Reply-To: andre.przywara-5wv7dgnIgG8@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: <1456165255-31013-1-git-send-email-andre.przywara-5wv7dgnIgG8@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Maxime Ripard , Chen-Yu Tsai , linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Cc: Arnd Bergmann , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org Now that we can reuse the A31 PLL6 clock driver for clocks other then PLL6 itself, describe the PLL8 clock properly. Signed-off-by: Andre Przywara --- arch/arm/boot/dts/sun8i-h3.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 3ba65c2..d84ea9b 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -137,12 +137,12 @@ clock-output-names = "pll6d2"; }; - /* dummy clock until pll6 can be reused */ - pll8: pll8_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1>; - clock-output-names = "pll8"; + pll8: clk@c01c20044 { + #clock-cells = <1>; + compatible = "allwinner,sun6i-a31-pll6-clk"; + reg = <0x01c20044 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll8", "pll8x2"; }; cpu: cpu_clk@01c20050 { @@ -243,7 +243,7 @@ #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; clock-output-names = "mmc0", "mmc0_output", "mmc0_sample"; @@ -253,7 +253,7 @@ #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; clock-output-names = "mmc1", "mmc1_output", "mmc1_sample"; @@ -263,7 +263,7 @@ #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; clock-output-names = "mmc2", "mmc2_output", "mmc2_sample"; -- 2.6.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755287AbcBVS0x (ORCPT ); Mon, 22 Feb 2016 13:26:53 -0500 Received: from foss.arm.com ([217.140.101.70]:59514 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752376AbcBVSVF (ORCPT ); Mon, 22 Feb 2016 13:21:05 -0500 From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , linux-sunxi@googlegroups.com Cc: Arnd Bergmann , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , devicetree@vger.kernel.org Subject: [PATCH v3 02/10] ARM: dts: sunxi: make PLL8 in the H3 a proper clock Date: Mon, 22 Feb 2016 18:20:47 +0000 Message-Id: <1456165255-31013-3-git-send-email-andre.przywara@arm.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1456165255-31013-1-git-send-email-andre.przywara@arm.com> References: <1456165255-31013-1-git-send-email-andre.przywara@arm.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that we can reuse the A31 PLL6 clock driver for clocks other then PLL6 itself, describe the PLL8 clock properly. Signed-off-by: Andre Przywara --- arch/arm/boot/dts/sun8i-h3.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 3ba65c2..d84ea9b 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -137,12 +137,12 @@ clock-output-names = "pll6d2"; }; - /* dummy clock until pll6 can be reused */ - pll8: pll8_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1>; - clock-output-names = "pll8"; + pll8: clk@c01c20044 { + #clock-cells = <1>; + compatible = "allwinner,sun6i-a31-pll6-clk"; + reg = <0x01c20044 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll8", "pll8x2"; }; cpu: cpu_clk@01c20050 { @@ -243,7 +243,7 @@ #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; clock-output-names = "mmc0", "mmc0_output", "mmc0_sample"; @@ -253,7 +253,7 @@ #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; clock-output-names = "mmc1", "mmc1_output", "mmc1_sample"; @@ -263,7 +263,7 @@ #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clocks = <&osc24M>, <&pll6 0>, <&pll8 0>; clock-output-names = "mmc2", "mmc2_output", "mmc2_sample"; -- 2.6.4