From: <gregkh@linuxfoundation.org>
To: cq.tang@intel.com, David.Woodhouse@intel.com, gregkh@linuxfoundation.org
Cc: <stable@vger.kernel.org>, <stable-commits@vger.kernel.org>
Subject: Patch "iommu/vt-d: Fix 64-bit accesses to 32-bit DMAR_GSTS_REG" has been added to the 4.4-stable tree
Date: Tue, 23 Feb 2016 19:24:29 -0800 [thread overview]
Message-ID: <14562842699221@kroah.com> (raw)
This is a note to let you know that I've just added the patch titled
iommu/vt-d: Fix 64-bit accesses to 32-bit DMAR_GSTS_REG
to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
iommu-vt-d-fix-64-bit-accesses-to-32-bit-dmar_gsts_reg.patch
and it can be found in the queue-4.4 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
>From fda3bec12d0979aae3f02ee645913d66fbc8a26e Mon Sep 17 00:00:00 2001
From: CQ Tang <cq.tang@intel.com>
Date: Wed, 13 Jan 2016 21:15:03 +0000
Subject: iommu/vt-d: Fix 64-bit accesses to 32-bit DMAR_GSTS_REG
From: CQ Tang <cq.tang@intel.com>
commit fda3bec12d0979aae3f02ee645913d66fbc8a26e upstream.
This is a 32-bit register. Apparently harmless on real hardware, but
causing justified warnings in simulation.
Signed-off-by: CQ Tang <cq.tang@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/iommu/dmar.c | 2 +-
drivers/iommu/intel_irq_remapping.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
--- a/drivers/iommu/dmar.c
+++ b/drivers/iommu/dmar.c
@@ -1347,7 +1347,7 @@ void dmar_disable_qi(struct intel_iommu
raw_spin_lock_irqsave(&iommu->register_lock, flags);
- sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
+ sts = readl(iommu->reg + DMAR_GSTS_REG);
if (!(sts & DMA_GSTS_QIES))
goto end;
--- a/drivers/iommu/intel_irq_remapping.c
+++ b/drivers/iommu/intel_irq_remapping.c
@@ -629,7 +629,7 @@ static void iommu_disable_irq_remapping(
raw_spin_lock_irqsave(&iommu->register_lock, flags);
- sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
+ sts = readl(iommu->reg + DMAR_GSTS_REG);
if (!(sts & DMA_GSTS_IRES))
goto end;
Patches currently in stable-queue which might be from cq.tang@intel.com are
queue-4.4/iommu-vt-d-fix-64-bit-accesses-to-32-bit-dmar_gsts_reg.patch
queue-4.4/iommu-vt-d-clear-ppr-bit-to-ensure-we-get-more-page-request-interrupts.patch
reply other threads:[~2016-02-24 3:44 UTC|newest]
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