From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752058AbcB2WR3 (ORCPT ); Mon, 29 Feb 2016 17:17:29 -0500 Received: from mail-bn1bon0085.outbound.protection.outlook.com ([157.56.111.85]:4184 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750832AbcB2WR1 (ORCPT ); Mon, 29 Feb 2016 17:17:27 -0500 Authentication-Results: alien8.de; dkim=none (message not signed) header.d=none;alien8.de; dmarc=none action=none header.from=amd.com; From: Aravind Gopalakrishnan To: , , , , , , CC: , , , , , , , , Subject: [PATCH V2 0/5] Updates to EDAC and AMD MCE driver Date: Mon, 29 Feb 2016 16:32:54 -0600 Message-ID: <1456785179-14378-1-git-send-email-Aravind.Gopalakrishnan@amd.com> X-Mailer: git-send-email 2.7.0 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: BLUPR11CA0023.namprd11.prod.outlook.com (10.141.240.33) To BY1PR12MB0424.namprd12.prod.outlook.com (25.162.147.13) X-MS-Office365-Filtering-Correlation-Id: fa0f3f8f-6bf1-4f5e-8f69-08d34156186f X-Microsoft-Exchange-Diagnostics: 1;BY1PR12MB0424;2:lhOXFuwOTdRo8oQ6o9uo75emAzjOMgyIzS9kZ87iXDcKZq39YVH//boDGXJ2qP/JpOXnTsNfTUx/VU9euN3n82tfwyGIK5i/x98YCOPt1OTwrKQYnP/fCIMZukI6nZb8ACu6nlNYM18kP/DBjJvWyJomIt59q6H7zMCoMOiTY8wPKC1gAQlW+hs8PwC7yros;3:LebWhyiAuU97ZTvBPr/93xXrOfv3ctqtHlQ1jmX571zoJVmOLZ+I+iIlC5AkEDZuYbvMHXMpjLQPkWTK7cJ7xLN/orfx3c+q+0USCoVCN+tAP+zSoshzezmSQkVvxbCa;25:h0Uz6gfZVNp5mOsaLgZPpaaki7lIg5LwkAJmq6xogtslzDrw5l9vhohHfORtCRXsWJAgcGYLda4NSyw57jC9niKBte+0kBbxglvcWgFK4U394DW8fMG0/JtJi4VmjX+QmQXi9BeqZskhQ4UYa0I8iSkoeix+riv3jWS4sb7PK/3hDMG20+CS0VPrAUf77JMCewkvqAgbXmMfp8yCEUm6625CQJyHKQkdiGyejEpQV4Gafbg7nMiKJHYpst/fEYgBil815g0Jgw7HtnxTtcn2rsWYEleX30cTyeb0nYWRQrMiBEq4V/tGMozvA8DFMxDJv1w6MS6i5ZRPXrm1ngxstg== X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY1PR12MB0424; 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Patches 1, 2 and 3 are meant for the upcoming processors. Patches 4 and 5 are either fixing or adding comments to help in understanding the code and do not introduce any functional changes. Patch 1: Move MSR definition to mce.h Patch 2: Updates to EDAC driver to decode the new error signatures Patch 3: Fix logic to obtain correct block address Patch 4: Fix deferred error comment Patch 5: Add comments to amd_nb.h to describe threshold_block structure Tested V2 patches for regressions on Fam15h, Fam10h systems and found none. Note 1: Introduced new patch for moving MCx_CONFIG MSR to mce.h Note 2: The enums ans amd_hwid_mappings[] array are placed in arch/x86 as there are follow-up patches which need the struct there Changes from V1: (per Boris suggestions) - Simplify error decoding routines - Move headers to mce.h - Rename enumerations and struct members (to be more descriptive) - Drop gerund usage - Remove comments that are spelling out the code Aravind Gopalakrishnan (5): x86/mce: Move MCx_CONFIG MSR definition EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors x86/mce/AMD: Fix logic to obtain block address x86/mce: Clarify comments regarding deferred error x86/mce/AMD: Add comments for easier understanding arch/x86/include/asm/amd_nb.h | 18 +- arch/x86/include/asm/mce.h | 63 ++++++- arch/x86/include/asm/msr-index.h | 4 - arch/x86/kernel/cpu/mcheck/mce_amd.c | 108 +++++++---- drivers/edac/mce_amd.c | 342 ++++++++++++++++++++++++++++++++++- 5 files changed, 486 insertions(+), 49 deletions(-) -- 2.7.0