From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754185AbcB2WRo (ORCPT ); Mon, 29 Feb 2016 17:17:44 -0500 Received: from mail-bn1bon0089.outbound.protection.outlook.com ([157.56.111.89]:4032 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753482AbcB2WRi (ORCPT ); Mon, 29 Feb 2016 17:17:38 -0500 Authentication-Results: alien8.de; dkim=none (message not signed) header.d=none;alien8.de; dmarc=none action=none header.from=amd.com; From: Aravind Gopalakrishnan To: , , , , , , CC: , , , , , , , , Subject: [PATCH V2 5/5] x86/mce/AMD: Add comments for easier understanding Date: Mon, 29 Feb 2016 16:32:59 -0600 Message-ID: <1456785179-14378-6-git-send-email-Aravind.Gopalakrishnan@amd.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1456785179-14378-1-git-send-email-Aravind.Gopalakrishnan@amd.com> References: <1456785179-14378-1-git-send-email-Aravind.Gopalakrishnan@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: BLUPR11CA0023.namprd11.prod.outlook.com (10.141.240.33) To BY1PR12MB0424.namprd12.prod.outlook.com (25.162.147.13) X-MS-Office365-Filtering-Correlation-Id: 7c9cf463-05b1-4867-69b2-08d341561ff8 X-Microsoft-Exchange-Diagnostics: 1;BY1PR12MB0424;2:KEGC5q7abP+cr8uBaTW3LYLLwTsBUXEEUNQVKEjdukzNBFI63YLuJ1LfTXAi/e7adVlduDj1eBCFoig2tVduepSrr3/PB32kd0BeXB9uS5XUuRCBs8NhOUgnuRG3uaFQTVC56qybHDQqE4U1XGUdMeUeWJG+U52+/XaBE67T+DbVRAZTDP2mjPAIQrfO/OTA;3:u0JQBm/IdVKeCmdqngPtQZerOrQVt3kYH+W1uFDR1JNPcQHnTgQn36w65hL1ySJiNGIpp4ViRxHJzY9WqBB20nXhZE6U/B05jnKorD7bBYBItY+L5Vm04RUFOqsYwUxx;25:ALuVe2XCGBxIx4mM1e1BrrTjElSzmYp8kKwP2aYU1pH3pN9UmOb8krNkUz2+EGSPDaN53+o+8pt+8qu8ylpyA0ly4vt65/IcauAzdMncH13TFDi2ifHHNQrDGEFW1yc+ph9FNhFzy+lOPXr1alYA9wSE95SNe+Po5lCmCpY7zcWgd4nTnBDr+rWBpttozgWNCCZXdDu5yDhC8drxOj8L/ZfCgPYTYnSofzFUsEe+kJXaDYA6SsxtJjexIklCg+UplbCgLe28ryWcIrp4k4WEXylqo1cJWPH8A/b7dEBnT+v1IJxQyrqO2Hl9/nwBADF0f97uIinRMa+7j8r7hb29vw== X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY1PR12MB0424; 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Also, trimming comments around threshold_restart_bank() and updating copyright info. No functional change is introduced. Signed-off-by: Aravind Gopalakrishnan --- arch/x86/include/asm/amd_nb.h | 18 +++++++++--------- arch/x86/kernel/cpu/mcheck/mce_amd.c | 7 ++----- 2 files changed, 11 insertions(+), 14 deletions(-) diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h index 3c56ef1..bc01c0a 100644 --- a/arch/x86/include/asm/amd_nb.h +++ b/arch/x86/include/asm/amd_nb.h @@ -27,15 +27,15 @@ struct amd_l3_cache { }; struct threshold_block { - unsigned int block; - unsigned int bank; - unsigned int cpu; - u32 address; - u16 interrupt_enable; - bool interrupt_capable; - u16 threshold_limit; - struct kobject kobj; - struct list_head miscj; + unsigned int block; /* Threshold block number within bank */ + unsigned int bank; /* MCA bank the block belongs to */ + unsigned int cpu; /* CPU which controls the MCA bank */ + u32 address; /* MSR address for the block */ + u16 interrupt_enable; /* Enable/ Disable APIC interrupt upon threshold error */ + bool interrupt_capable; /* Specifies if interrupt is possible from the block */ + u16 threshold_limit; /* Value upon which threshold interrupt is generated */ + struct kobject kobj; /* sysfs object */ + struct list_head miscj; /* Add multiple threshold blocks within a bank to the list */ }; struct threshold_bank { diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index a155eaa..ebb63ec 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -1,5 +1,5 @@ /* - * (c) 2005-2015 Advanced Micro Devices, Inc. + * (c) 2005-2016 Advanced Micro Devices, Inc. * Your use of this code is subject to the terms and conditions of the * GNU general public license version 2. See "COPYING" or * http://www.gnu.org/licenses/gpl.html @@ -183,10 +183,7 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) return 1; }; -/* - * Called via smp_call_function_single(), must be called with correct - * cpu affinity. - */ +/* Reprogram MCx_MISC MSR behind this threshold bank */ static void threshold_restart_bank(void *_tr) { struct thresh_restart *tr = _tr; -- 2.7.0