All of lore.kernel.org
 help / color / mirror / Atom feed
From: Ander Conselvan De Oliveira <conselvan2@gmail.com>
To: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 13/13] drm/i915: Make SKL/KBL DPLL0 managed by the shared dpll code
Date: Wed, 09 Mar 2016 11:57:54 +0200	[thread overview]
Message-ID: <1457517474.2763.51.camel@gmail.com> (raw)
In-Reply-To: <56DFE075.2000005@linux.intel.com>

On Wed, 2016-03-09 at 09:36 +0100, Maarten Lankhorst wrote:
> Op 08-03-16 om 16:46 schreef Ander Conselvan de Oliveira:
> > Include DPLL0 in the managed dplls for SKL/KBL. While it has to be kept
> > enabled because of it driving CDCLK, it is better to special case that
> > inside the DPLL code than in the higher level.
> > 
> > v2: Use INTEL_DPLL_ALWAYS_ON flag. (Ander)
> > 
> > v3: Remove extremely paranoid WARN_ONs. (Maarten)
> >     Handle DPLL0 in skylake_get_ddi_pll() properly. (Ander)
> > 
> > Signed-off-by: Ander Conselvan de Oliveira <
> > ander.conselvan.de.oliveira@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c      |  21 ------
> >  drivers/gpu/drm/i915/intel_display.c  |  12 +---
> >  drivers/gpu/drm/i915/intel_dp.c       |  52 +-------------
> >  drivers/gpu/drm/i915/intel_dpll_mgr.c | 124 ++++++++++++++++++++++++++-----
> > ---
> >  drivers/gpu/drm/i915/intel_dpll_mgr.h |   7 +-
> >  5 files changed, 105 insertions(+), 111 deletions(-)
> Excellent, glad you managed to test it. :)
> > @@ -1176,6 +1221,19 @@ skl_get_dpll(struct intel_crtc *crtc, struct
> > intel_crtc_state *crtc_state,
> >  		case 270000:
> >  			ctrl1 |=
> > DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
> >  			break;
> > +		/* eDP 1.4 rates */
> > +		case 162000:
> > +			ctrl1 |=
> > DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
> > +			break;
> > +		/* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is
> > 8640 which
> > +		results in CDCLK change. Need to handle the change of CDCLK
> > by
> > +		disabling pipes and re-enabling them */
> > +		case 108000:
> > +			ctrl1 |=
> > DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
> > +			break;
> > +		case 216000:
> > +			ctrl1 |=
> > DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
> > +			break;
> >  		}
> >  
> >  		cfgcr1 = cfgcr2 = 0;
> > 
> Seems there's already a patch to address this on the mailing list, so for 12
> and 13:
> 
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

Whole series merged. Thanks for reviewing.

Ander

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2016-03-09  9:57 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-08 15:46 [PATCH 00/13] Shared pll improvements Ander Conselvan de Oliveira
2016-03-08 15:46 ` [PATCH 01/13] drm/i915: Move shared dpll code to a new file Ander Conselvan de Oliveira
2016-03-08 15:46 ` [PATCH 02/13] drm/i915: Move ddi shared dpll code to intel_dpll_mgr.c Ander Conselvan de Oliveira
2016-03-08 15:46 ` [PATCH 03/13] drm/i915: Split intel_get_shared_dpll() into smaller functions Ander Conselvan de Oliveira
2016-03-08 15:46 ` [PATCH 04/13] drm/i915: Store a direct pointer to shared dpll in intel_crtc_state Ander Conselvan de Oliveira
2016-03-08 15:46 ` [PATCH 05/13] drm/i915: Move shared dpll struct definitions to separate header file Ander Conselvan de Oliveira
2016-03-08 15:46 ` [PATCH 06/13] drm/i915: Move shared dpll function prototypes to intel_dpll_mgr.h Ander Conselvan de Oliveira
2016-03-08 15:46 ` [PATCH 07/13] drm/i915: Use a table to initilize shared dplls Ander Conselvan de Oliveira
2016-03-08 15:46 ` [PATCH 08/13] drm/i915: Refactor platform specifics out of intel_get_shared_dpll() Ander Conselvan de Oliveira
2016-03-08 15:46 ` [PATCH 09/13] drm/i915: Move HSW/BDW pll selection logic to intel_dpll_mgr.c Ander Conselvan de Oliveira
2016-03-08 15:46 ` [PATCH 10/13] drm/i915: Move SKL/KLB " Ander Conselvan de Oliveira
2016-03-08 15:46 ` [PATCH 11/13] drm/i915: Move BXT pll configuration " Ander Conselvan de Oliveira
2016-03-08 15:46 ` [PATCH 12/13] drm/i915: Manage HSW/BDW LCPLLs with the shared dpll interface Ander Conselvan de Oliveira
2016-03-08 15:46 ` [PATCH 13/13] drm/i915: Make SKL/KBL DPLL0 managed by the shared dpll code Ander Conselvan de Oliveira
2016-03-09  8:36   ` Maarten Lankhorst
2016-03-09  9:57     ` Ander Conselvan De Oliveira [this message]
2016-03-08 16:01 ` ✗ Fi.CI.BAT: warning for Shared pll improvements (rev4) Patchwork
2016-03-09  9:08   ` Conselvan De Oliveira, Ander
  -- strict thread matches above, loose matches on Subject: below --
2016-02-26 13:54 [PATCH 00/13] Shared pll improvements Ander Conselvan de Oliveira
2016-02-26 13:54 ` [PATCH 13/13] drm/i915: Make SKL/KBL DPLL0 managed by the shared dpll code Ander Conselvan de Oliveira

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1457517474.2763.51.camel@gmail.com \
    --to=conselvan2@gmail.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=maarten.lankhorst@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.