From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>
Subject: [PATCH v2 05/17] drm/i915: Move load time init of clock gating hooks earlier
Date: Fri, 11 Mar 2016 18:31:30 +0200 [thread overview]
Message-ID: <1457713902-2425-6-git-send-email-imre.deak@intel.com> (raw)
In-Reply-To: <1457713902-2425-1-git-send-email-imre.deak@intel.com>
Split out the part initing the clock gating hooks and move it earlier.
Add a new NOP hook for platforms without the need to apply clockgating
or workaround settings, so that the hook can be called unconditionally.
Also add a WARN for future platforms that forget to add a hook.
The rest of the hooks in intel_init_pm() should be inited in the same
way, but atm some of the hooks are set only conditionally, so before
doing this we need to make the setup unconditional and use instead some
flags.
v2:
- add a NOP hook and WARN if no hook is set for the platform (Chris)
- use the term hook instead of callback for these functions (Jani)
CC: Jani Nikula <jani.nikula@intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_dma.c | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 93 +++++++++++++++++++++++++---------------
3 files changed, 60 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 44f15de..60e8fe6 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1029,6 +1029,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
intel_power_domains_init(dev_priv);
intel_irq_init(dev_priv);
intel_init_display_hooks(dev_priv);
+ intel_init_clock_gating_hooks(dev_priv);
intel_init_audio_hooks(dev_priv);
intel_runtime_pm_get(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d0f05a8..7a642ae 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1587,6 +1587,7 @@ void intel_suspend_hw(struct drm_device *dev);
int ilk_wm_max_level(const struct drm_device *dev);
void intel_update_watermarks(struct drm_crtc *crtc);
void intel_init_pm(struct drm_device *dev);
+void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
void intel_pm_setup(struct drm_device *dev);
void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
void intel_gpu_ips_teardown(void);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d7aef17..49366da 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7097,8 +7097,7 @@ void intel_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- if (dev_priv->display.init_clock_gating)
- dev_priv->display.init_clock_gating(dev);
+ dev_priv->display.init_clock_gating(dev);
}
void intel_suspend_hw(struct drm_device *dev)
@@ -7107,6 +7106,63 @@ void intel_suspend_hw(struct drm_device *dev)
lpt_suspend_hw(dev);
}
+static void nop_init_clock_gating(struct drm_device *dev)
+{
+ DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
+}
+
+/**
+ * intel_init_clock_gating_hooks - setup the clock gating hooks
+ * @dev_priv: device private
+ *
+ * Setup the hooks that configure which clocks of a given platform can be
+ * gated and also apply various GT and display specific workarounds for these
+ * platforms. Note that some GT specific workarounds are applied separately
+ * when GPU contexts or batchbuffers start their execution.
+ */
+void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
+{
+ if (IS_SKYLAKE(dev_priv))
+ dev_priv->display.init_clock_gating = nop_init_clock_gating;
+ else if (IS_KABYLAKE(dev_priv))
+ dev_priv->display.init_clock_gating = nop_init_clock_gating;
+ else if (IS_BROXTON(dev_priv))
+ dev_priv->display.init_clock_gating = bxt_init_clock_gating;
+ else if (IS_BROADWELL(dev_priv))
+ dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
+ else if (IS_CHERRYVIEW(dev_priv))
+ dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
+ else if (IS_HASWELL(dev_priv))
+ dev_priv->display.init_clock_gating = haswell_init_clock_gating;
+ else if (IS_IVYBRIDGE(dev_priv))
+ dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
+ else if (IS_VALLEYVIEW(dev_priv))
+ dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
+ else if (IS_GEN6(dev_priv))
+ dev_priv->display.init_clock_gating = gen6_init_clock_gating;
+ else if (IS_GEN5(dev_priv))
+ dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
+ else if (IS_G4X(dev_priv))
+ dev_priv->display.init_clock_gating = g4x_init_clock_gating;
+ else if (IS_CRESTLINE(dev_priv))
+ dev_priv->display.init_clock_gating = crestline_init_clock_gating;
+ else if (IS_BROADWATER(dev_priv))
+ dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
+ else if (IS_GEN4(dev_priv))
+ dev_priv->display.init_clock_gating = nop_init_clock_gating;
+ else if (IS_GEN3(dev_priv))
+ dev_priv->display.init_clock_gating = gen3_init_clock_gating;
+ else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
+ dev_priv->display.init_clock_gating = i85x_init_clock_gating;
+ else if (IS_GEN2(dev_priv))
+ dev_priv->display.init_clock_gating = i830_init_clock_gating;
+ else {
+ MISSING_CASE(INTEL_DEVID(dev_priv));
+ dev_priv->display.init_clock_gating = nop_init_clock_gating;
+ }
+
+}
+
/* Set up chip specific power management-related functions */
void intel_init_pm(struct drm_device *dev)
{
@@ -7123,10 +7179,6 @@ void intel_init_pm(struct drm_device *dev)
/* For FIFO watermark updates */
if (INTEL_INFO(dev)->gen >= 9) {
skl_setup_wm_latency(dev);
-
- if (IS_BROXTON(dev))
- dev_priv->display.init_clock_gating =
- bxt_init_clock_gating;
dev_priv->display.update_wm = skl_update_wm;
} else if (HAS_PCH_SPLIT(dev)) {
ilk_setup_wm_latency(dev);
@@ -7146,29 +7198,12 @@ void intel_init_pm(struct drm_device *dev)
DRM_DEBUG_KMS("Failed to read display plane latency. "
"Disable CxSR\n");
}
-
- if (IS_GEN5(dev))
- dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
- else if (IS_GEN6(dev))
- dev_priv->display.init_clock_gating = gen6_init_clock_gating;
- else if (IS_IVYBRIDGE(dev))
- dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
- else if (IS_HASWELL(dev))
- dev_priv->display.init_clock_gating = haswell_init_clock_gating;
- else if (INTEL_INFO(dev)->gen == 8)
- dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
} else if (IS_CHERRYVIEW(dev)) {
vlv_setup_wm_latency(dev);
-
dev_priv->display.update_wm = vlv_update_wm;
- dev_priv->display.init_clock_gating =
- cherryview_init_clock_gating;
} else if (IS_VALLEYVIEW(dev)) {
vlv_setup_wm_latency(dev);
-
dev_priv->display.update_wm = vlv_update_wm;
- dev_priv->display.init_clock_gating =
- valleyview_init_clock_gating;
} else if (IS_PINEVIEW(dev)) {
if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
dev_priv->is_ddr3,
@@ -7184,20 +7219,13 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->display.update_wm = NULL;
} else
dev_priv->display.update_wm = pineview_update_wm;
- dev_priv->display.init_clock_gating = gen3_init_clock_gating;
} else if (IS_G4X(dev)) {
dev_priv->display.update_wm = g4x_update_wm;
- dev_priv->display.init_clock_gating = g4x_init_clock_gating;
} else if (IS_GEN4(dev)) {
dev_priv->display.update_wm = i965_update_wm;
- if (IS_CRESTLINE(dev))
- dev_priv->display.init_clock_gating = crestline_init_clock_gating;
- else if (IS_BROADWATER(dev))
- dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
} else if (IS_GEN3(dev)) {
dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
- dev_priv->display.init_clock_gating = gen3_init_clock_gating;
} else if (IS_GEN2(dev)) {
if (INTEL_INFO(dev)->num_pipes == 1) {
dev_priv->display.update_wm = i845_update_wm;
@@ -7206,11 +7234,6 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i830_get_fifo_size;
}
-
- if (IS_I85X(dev) || IS_I865G(dev))
- dev_priv->display.init_clock_gating = i85x_init_clock_gating;
- else
- dev_priv->display.init_clock_gating = i830_init_clock_gating;
} else {
DRM_ERROR("unexpected fall-through in intel_init_pm\n");
}
--
2.5.0
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next prev parent reply other threads:[~2016-03-11 16:31 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-11 16:31 [PATCH 00/17] drm/i915: Split driver init step to phases Imre Deak
2016-03-11 16:31 ` [PATCH v2 01/17] Fix MCHBAR cleanup on the driver init error path Imre Deak
2016-03-15 6:30 ` David Weinehall
2016-03-11 16:31 ` [PATCH v2 02/17] drm/i915: Move load time PCH detect, DPIO, power domain SW init earlier Imre Deak
2016-03-11 16:31 ` [PATCH v2 03/17] drm/i915: Move load time IRQ " Imre Deak
2016-03-11 16:31 ` [PATCH v2 04/17] drm/i915: Move load time init of display/audio hooks earlier Imre Deak
2016-03-11 16:31 ` Imre Deak [this message]
2016-03-11 19:57 ` [PATCH v2 05/17] drm/i915: Move load time init of clock gating " Chris Wilson
2016-03-11 20:12 ` Imre Deak
2016-03-11 20:28 ` [PATCH v3] " Imre Deak
2016-03-11 16:31 ` [PATCH v2 06/17] drm/i915: Move load time runtime device info init earlier Imre Deak
2016-03-11 16:31 ` [PATCH v2 07/17] drm/i915: Move load time gem_load_init earlier Imre Deak
2016-03-11 16:31 ` [PATCH v2 08/17] drm/i915: Move load time runtime PM get later Imre Deak
2016-03-11 16:31 ` [PATCH v2 09/17] drm/i915: Move load time shrinker registration later Imre Deak
2016-03-11 16:31 ` [PATCH v2 10/17] drm/i915: Move load time audio component registration earlier Imre Deak
2016-03-11 16:31 ` [PATCH v2 11/17] drm/i915: Move unload time display power domain uninit later Imre Deak
2016-03-11 16:31 ` [PATCH v2 12/17] drm/i915: Move unload time GTT, MSI IRQ cleanup later Imre Deak
2016-03-11 16:31 ` [PATCH v2 13/17] drm/i915: Move unload time opregion unregistration earlier Imre Deak
2016-03-11 16:31 ` [PATCH v2 14/17] drm/i915: Split out load time early initialization Imre Deak
2016-03-11 16:31 ` [PATCH v2 15/17] drm/i915: Split out load time MMIO initialization Imre Deak
2016-03-11 16:31 ` [PATCH v2 16/17] drm/i915: Split out load time HW initialization Imre Deak
2016-03-11 16:31 ` [PATCH v2 17/17] drm/i915: Split out load time interface registration Imre Deak
2016-03-11 19:55 ` Chris Wilson
2016-03-11 20:11 ` Imre Deak
2016-03-11 20:38 ` Chris Wilson
2016-03-11 20:51 ` Imre Deak
2016-03-11 20:34 ` [PATCH v3 " Imre Deak
2016-03-14 11:00 ` [PATCH v4 " Imre Deak
2016-03-15 8:45 ` Daniel Vetter
2016-03-12 7:31 ` ✗ Fi.CI.BAT: failure for drm/i915: Split driver init step to phases (rev3) Patchwork
2016-03-14 11:33 ` ✗ Fi.CI.BAT: failure for drm/i915: Split driver init step to phases (rev4) Patchwork
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