From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linuxfoundation.org ([140.211.169.12]:50209 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756070AbcDJSBE (ORCPT ); Sun, 10 Apr 2016 14:01:04 -0400 Subject: Patch "clk: bcm2835: Fix setting of PLL divider clock rates" has been added to the 4.4-stable tree To: eric@anholt.net, gregkh@linuxfoundation.org, mturquette@baylibre.com Cc: , From: Date: Sun, 10 Apr 2016 11:01:02 -0700 Message-ID: <1460311262179127@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: This is a note to let you know that I've just added the patch titled clk: bcm2835: Fix setting of PLL divider clock rates to the 4.4-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: clk-bcm2835-fix-setting-of-pll-divider-clock-rates.patch and it can be found in the queue-4.4 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >>From 773b3966dd3cdaeb68e7f2edfe5656abac1dc411 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 15 Feb 2016 19:03:57 -0800 Subject: clk: bcm2835: Fix setting of PLL divider clock rates From: Eric Anholt commit 773b3966dd3cdaeb68e7f2edfe5656abac1dc411 upstream. Our dividers weren't being set successfully because CM_PASSWORD wasn't included in the register write. It looks easier to just compute the divider to write ourselves than to update clk-divider for the ability to OR in some arbitrary bits on write. Fixes about half of the video modes on my HDMI monitor (everything except 720x400). Signed-off-by: Eric Anholt Signed-off-by: Michael Turquette Signed-off-by: Greg Kroah-Hartman --- drivers/clk/bcm/clk-bcm2835.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -1097,13 +1097,15 @@ static int bcm2835_pll_divider_set_rate( struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); struct bcm2835_cprman *cprman = divider->cprman; const struct bcm2835_pll_divider_data *data = divider->data; - u32 cm; - int ret; + u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS; - ret = clk_divider_ops.set_rate(hw, rate, parent_rate); - if (ret) - return ret; + div = DIV_ROUND_UP_ULL(parent_rate, rate); + div = min(div, max_div); + if (div == max_div) + div = 0; + + cprman_write(cprman, data->a2w_reg, div); cm = cprman_read(cprman, data->cm_reg); cprman_write(cprman, data->cm_reg, cm | data->load_mask); cprman_write(cprman, data->cm_reg, cm & ~data->load_mask); Patches currently in stable-queue which might be from eric@anholt.net are queue-4.4/clk-bcm2835-fix-setting-of-pll-divider-clock-rates.patch queue-4.4/pinctrl-bcm2835-fix-cut-and-paste-error-in-pull-parsing.patch