From: <gregkh@linuxfoundation.org>
To: eric@anholt.net, gregkh@linuxfoundation.org, mturquette@baylibre.com
Cc: <stable@vger.kernel.org>, <stable-commits@vger.kernel.org>
Subject: Patch "clk: bcm2835: Fix setting of PLL divider clock rates" has been added to the 4.5-stable tree
Date: Sun, 10 Apr 2016 11:01:10 -0700 [thread overview]
Message-ID: <146031127020410@kroah.com> (raw)
This is a note to let you know that I've just added the patch titled
clk: bcm2835: Fix setting of PLL divider clock rates
to the 4.5-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
clk-bcm2835-fix-setting-of-pll-divider-clock-rates.patch
and it can be found in the queue-4.5 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
>From 773b3966dd3cdaeb68e7f2edfe5656abac1dc411 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 15 Feb 2016 19:03:57 -0800
Subject: clk: bcm2835: Fix setting of PLL divider clock rates
From: Eric Anholt <eric@anholt.net>
commit 773b3966dd3cdaeb68e7f2edfe5656abac1dc411 upstream.
Our dividers weren't being set successfully because CM_PASSWORD wasn't
included in the register write. It looks easier to just compute the
divider to write ourselves than to update clk-divider for the ability
to OR in some arbitrary bits on write.
Fixes about half of the video modes on my HDMI monitor (everything
except 720x400).
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/clk/bcm/clk-bcm2835.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1107,13 +1107,15 @@ static int bcm2835_pll_divider_set_rate(
struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
struct bcm2835_cprman *cprman = divider->cprman;
const struct bcm2835_pll_divider_data *data = divider->data;
- u32 cm;
- int ret;
+ u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS;
- ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
- if (ret)
- return ret;
+ div = DIV_ROUND_UP_ULL(parent_rate, rate);
+ div = min(div, max_div);
+ if (div == max_div)
+ div = 0;
+
+ cprman_write(cprman, data->a2w_reg, div);
cm = cprman_read(cprman, data->cm_reg);
cprman_write(cprman, data->cm_reg, cm | data->load_mask);
cprman_write(cprman, data->cm_reg, cm & ~data->load_mask);
Patches currently in stable-queue which might be from eric@anholt.net are
queue-4.5/clk-bcm2835-fix-setting-of-pll-divider-clock-rates.patch
queue-4.5/pinctrl-bcm2835-fix-cut-and-paste-error-in-pull-parsing.patch
queue-4.5/drm-vc4-return-efault-on-copy_from_user-failure.patch
reply other threads:[~2016-04-10 18:01 UTC|newest]
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