From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Alexey Brodkin To: Jose Abreu CC: "linux-kernel@vger.kernel.org" , "robh+dt@kernel.org" , "mturquette@baylibre.com" , Carlos Palminha , "devicetree@vger.kernel.org" , "linux-snps-arc@lists.infradead.org" , Vineet Gupta , "linux-clk@vger.kernel.org" , "sboyd@codeaurora.org" Subject: Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver Date: Mon, 11 Apr 2016 16:47:51 +0000 Message-ID: <1460393270.5119.20.camel@synopsys.com> References: <50c75be8ecab225a1dd49628a173d211a02755b2.1459791946.git.joabreu@synopsys.com> In-Reply-To: <50c75be8ecab225a1dd49628a173d211a02755b2.1459791946.git.joabreu@synopsys.com> Content-Type: text/plain; charset="utf-7" MIME-Version: 1.0 List-ID: Hi Jose, On Mon, 2016-04-11 at 11:41 +-0100, Jose Abreu wrote: +AD4- The ARC SDP I2S clock can be programmed using a +AD4- specific PLL. +AD4-=20 +AD4- This patch has the goal of adding a clock driver +AD4- that programs this PLL. +AD4-=20 +AD4- At this moment the rate values are hardcoded in +AD4- a table but in the future it would be ideal to +AD4- use a function which determines the PLL values +AD4- given the desired rate. +AD4-=20 +AD4- Signed-off-by: Jose Abreu +ADw-joabreu+AEA-synopsys.com+AD4- +AD4- --- +AD4-=20 +AD4- Changes v3 -+AD4- v4: +AD4- +ACo- Added binding document (as suggested by Stephen Boyd) +AD4- +ACo- Minor code style fixes (as suggested by Stephen Boyd) +AD4- +ACo- Use ioremap (as suggested by Stephen Boyd) +AD4- +ACo- Implement round+AF8-rate (as suggested by Stephen Boyd) +AD4- +ACo- Change to platform driver (as suggested by Stephen Boyd) +AD4- +ACo- Use +AHs-readl/writel+AH0AXw-relaxed (as suggested by Vineet Gu= pta) +AD4-=20 +AD4- Changes v2 -+AD4- v3: +AD4- +ACo- Implemented recalc+AF8-rate +AD4-=20 +AD4- Changes v1 -+AD4- v2: +AD4- +ACo- Renamed folder to axs10x (as suggested by Alexey Brodkin) +AD4- +ACo- Added more supported rates +AFs-snip+AF0- +AD4- diff --git a/Documentation/devicetree/bindings/clock/i2s-pll-clock.tx= t b/Documentation/devicetree/bindings/clock/i2s- +AD4- pll-clock.txt +AD4- new file mode 100644 +AD4- index 0000000..ff86a41 +AD4- --- /dev/null +AD4- +-+-+- b/Documentation/devicetree/bindings/clock/i2s-pll-clock.txt +AD4- +AEAAQA- -0,0 +-1,17 +AEAAQA- +AD4- +-Binding for the AXS10X I2S PLL clock +AD4- +- +AD4- +-This binding uses the common clock binding+AFs-1+AF0-. +AD4- +- +AD4- +-+AFs-1+AF0- Documentation/devicetree/bindings/clock/clock-bindings.= txt +AD4- +- +AD4- +-Required properties: +AD4- +-- compatible: shall be +ACI-snps,i2s-pll-clock+ACI- +AD4- +-- +ACM-clock-cells: from common clock binding+ADs- Should always be= set to 0. +AD4- +-- reg : Address and length of the I2S PLL register set. +AD4- +- +AD4- +-Example: +AD4- +- clock+AEA-0x100a0 +AHs- Please remove +ACI-0x+ACI- from node name. +AD4- +- compatible +AD0- +ACI-snps,i2s-pll-clock+ACIAOw- +AD4- +- reg +AD0- +ADw-0x100a0 0x10+AD4AOw- +AD4- +- +ACM-clock-cells +AD0- +ADw-0+AD4AOw- +AD4- +- +AH0AOw- +AD4- diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile +AD4- index 46869d6..2ca62dc6 100644 +AD4- --- a/drivers/clk/Makefile +AD4- +-+-+- b/drivers/clk/Makefile +AD4- +AEAAQA- -84,3 +-84,4 +AEAAQA- obj-+ACQ-(CONFIG+AF8-X86) +-+AD0- x8= 6/ +AD4- +AKA-obj-+ACQ-(CONFIG+AF8-ARCH+AF8-ZX) +-+AD0- zte/ +AD4- +AKA-obj-+ACQ-(CONFIG+AF8-ARCH+AF8-ZYNQ) +-+AD0- zynq/ +AD4- +AKA-obj-+ACQ-(CONFIG+AF8-H8300) +-+AD0- h8300/ +AD4- +-obj-+ACQ-(CONFIG+AF8-ARC+AF8-PLAT+AF8-AXS10X) +-+AD0- axs10x/ +AD4- diff --git a/drivers/clk/axs10x/Makefile b/drivers/clk/axs10x/Makefil= e +AD4- new file mode 100644 +AD4- index 0000000..01996b8 +AD4- --- /dev/null +AD4- +-+-+- b/drivers/clk/axs10x/Makefile +AD4- +AEAAQA- -0,0 +-1 +AEAAQA- +AD4- +-obj-y +-+AD0- i2s+AF8-pll+AF8-clock.o +AD4- diff --git a/drivers/clk/axs10x/i2s+AF8-pll+AF8-clock.c b/drivers/clk= /axs10x/i2s+AF8-pll+AF8-clock.c +AD4- new file mode 100644 +AD4- index 0000000..3ba4e2f +AD4- --- /dev/null +AD4- +-+-+- b/drivers/clk/axs10x/i2s+AF8-pll+AF8-clock.c +AD4- +AEAAQA- -0,0 +-1,217 +AEAAQA- +AD4- +-/+ACo- +AD4- +- +ACo- Synopsys AXS10X SDP I2S PLL clock driver +AD4- +- +ACo- +AD4- +- +ACo- Copyright (C) 2016 Synopsys +AD4- +- +ACo- +AD4- +- +ACo- This file is licensed under the terms of the GNU General Pub= lic +AD4- +- +ACo- License version 2. This program is licensed +ACI-as is+ACI- = without any +AD4- +- +ACo- warranty of any kind, whether express or implied. +AD4- +- +ACo-/ +AD4- +- +AD4- +-+ACM-include +ADw-linux/platform+AF8-device.h+AD4- +AD4- +-+ACM-include +ADw-linux/module.h+AD4- +AD4- +-+ACM-include +ADw-linux/clk-provider.h+AD4- +AD4- +-+ACM-include +ADw-linux/err.h+AD4- +AD4- +-+ACM-include +ADw-linux/device.h+AD4- +ACI-linux/platform+AF8-device.h+ACI- includes +ACI-linux/device.h+ACI- so = you may make this list of headers a little bit shorter. +AD4- +-+ACM-include +ADw-linux/of+AF8-address.h+AD4- +AD4- +-+ACM-include +ADw-linux/slab.h+AD4- +AD4- +-+ACM-include +ADw-linux/of.h+AD4- +ACI-linux/of+AF8-address.h+ACI- already includes +ACI-linux/of.h+ACI-. +AFs-snip+AF0- +AD4- +- +AD4- +-static const struct of+AF8-device+AF8-id i2s+AF8-pll+AF8-clk+AF8-id= +AFsAXQ- +AD0- +AHs- +AD4- +- +AHs- .compatible +AD0- +ACI-snps,i2s-pll-clock+ACI-, +AH0-, I would think that it makes sense to add the board name in this compatible string. So something like+AKAAIg-snps,axs10x-i2s-pll-clock+= ACI- IMHO looks much more informative. Also adding Rob Herring and DT mailing list in Cc. Please make sure Rod acks your bindings and corresponding docs. -Alexey= From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexey.Brodkin@synopsys.com (Alexey Brodkin) Date: Mon, 11 Apr 2016 16:47:51 +0000 Subject: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver In-Reply-To: <50c75be8ecab225a1dd49628a173d211a02755b2.1459791946.git.joabreu@synopsys.com> References: <50c75be8ecab225a1dd49628a173d211a02755b2.1459791946.git.joabreu@synopsys.com> List-ID: Message-ID: <1460393270.5119.20.camel@synopsys.com> To: linux-snps-arc@lists.infradead.org Hi Jose, On Mon, 2016-04-11@11:41 +0100, Jose Abreu wrote: > The ARC SDP I2S clock can be programmed using a > specific PLL. > > This patch has the goal of adding a clock driver > that programs this PLL. > > At this moment the rate values are hardcoded in > a table but in the future it would be ideal to > use a function which determines the PLL values > given the desired rate. > > Signed-off-by: Jose Abreu > --- > > Changes v3 -> v4: > * Added binding document (as suggested by Stephen Boyd) > * Minor code style fixes (as suggested by Stephen Boyd) > * Use ioremap (as suggested by Stephen Boyd) > * Implement round_rate (as suggested by Stephen Boyd) > * Change to platform driver (as suggested by Stephen Boyd) > * Use {readl/writel}_relaxed (as suggested by Vineet Gupta) > > Changes v2 -> v3: > * Implemented recalc_rate > > Changes v1 -> v2: > * Renamed folder to axs10x (as suggested by Alexey Brodkin) > * Added more supported rates [snip] > diff --git a/Documentation/devicetree/bindings/clock/i2s-pll-clock.txt b/Documentation/devicetree/bindings/clock/i2s- > pll-clock.txt > new file mode 100644 > index 0000000..ff86a41 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/i2s-pll-clock.txt > @@ -0,0 +1,17 @@ > +Binding for the AXS10X I2S PLL clock > + > +This binding uses the common clock binding[1]. > + > +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt > + > +Required properties: > +- compatible: shall be "snps,i2s-pll-clock" > +- #clock-cells: from common clock binding; Should always be set to 0. > +- reg : Address and length of the I2S PLL register set. > + > +Example: > + clock at 0x100a0 { Please remove "0x" from node name. > + compatible = "snps,i2s-pll-clock"; > + reg = <0x100a0 0x10>; > + #clock-cells = <0>; > + }; > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile > index 46869d6..2ca62dc6 100644 > --- a/drivers/clk/Makefile > +++ b/drivers/clk/Makefile > @@ -84,3 +84,4 @@ obj-$(CONFIG_X86) += x86/ > ?obj-$(CONFIG_ARCH_ZX) += zte/ > ?obj-$(CONFIG_ARCH_ZYNQ) += zynq/ > ?obj-$(CONFIG_H8300) += h8300/ > +obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/ > diff --git a/drivers/clk/axs10x/Makefile b/drivers/clk/axs10x/Makefile > new file mode 100644 > index 0000000..01996b8 > --- /dev/null > +++ b/drivers/clk/axs10x/Makefile > @@ -0,0 +1 @@ > +obj-y += i2s_pll_clock.o > diff --git a/drivers/clk/axs10x/i2s_pll_clock.c b/drivers/clk/axs10x/i2s_pll_clock.c > new file mode 100644 > index 0000000..3ba4e2f > --- /dev/null > +++ b/drivers/clk/axs10x/i2s_pll_clock.c > @@ -0,0 +1,217 @@ > +/* > + * Synopsys AXS10X SDP I2S PLL clock driver > + * > + * Copyright (C) 2016 Synopsys > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +#include > +#include > +#include > +#include > +#include "linux/platform_device.h" includes "linux/device.h" so you may make this list of headers a little bit shorter. > +#include > +#include > +#include "linux/of_address.h" already includes "linux/of.h". [snip] > + > +static const struct of_device_id i2s_pll_clk_id[] = { > + { .compatible = "snps,i2s-pll-clock", }, I would think that it makes sense to add the board name in this compatible string. So something like?"snps,axs10x-i2s-pll-clock" IMHO looks much more informative. Also adding Rob Herring and DT mailing list in Cc. Please make sure Rod acks your bindings and corresponding docs. -Alexey From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexey Brodkin Subject: Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver Date: Mon, 11 Apr 2016 16:47:51 +0000 Message-ID: <1460393270.5119.20.camel@synopsys.com> References: <50c75be8ecab225a1dd49628a173d211a02755b2.1459791946.git.joabreu@synopsys.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-7" Content-Transfer-Encoding: 8BIT Return-path: In-Reply-To: <50c75be8ecab225a1dd49628a173d211a02755b2.1459791946.git.joabreu-HKixBCOQz3hWk0Htik3J/w@public.gmane.org> Content-Language: en-US Content-ID: <326FDFAA055727429000EC50BBEA85FF-z7JfP6tgrtVBCHUSTMH8dZqQE7yCjDx5@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Jose Abreu Cc: "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" , "mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org" , Carlos Palminha , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-snps-arc-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , Vineet Gupta , "linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org" List-Id: devicetree@vger.kernel.org Hi Jose, On Mon, 2016-04-11 at 11:41 +-0100, Jose Abreu wrote: +AD4- The ARC SDP I2S clock can be programmed using a +AD4- specific PLL. +AD4- +AD4- This patch has the goal of adding a clock driver +AD4- that programs this PLL. +AD4- +AD4- At this moment the rate values are hardcoded in +AD4- a table but in the future it would be ideal to +AD4- use a function which determines the PLL values +AD4- given the desired rate. +AD4- +AD4- Signed-off-by: Jose Abreu +ADw-joabreu+AEA-synopsys.com+AD4- +AD4- --- +AD4- +AD4- Changes v3 -+AD4- v4: +AD4- +ACo- Added binding document (as suggested by Stephen Boyd) +AD4- +ACo- Minor code style fixes (as suggested by Stephen Boyd) +AD4- +ACo- Use ioremap (as suggested by Stephen Boyd) +AD4- +ACo- Implement round+AF8-rate (as suggested by Stephen Boyd) +AD4- +ACo- Change to platform driver (as suggested by Stephen Boyd) +AD4- +ACo- Use +AHs-readl/writel+AH0AXw-relaxed (as suggested by Vineet Gupta) +AD4- +AD4- Changes v2 -+AD4- v3: +AD4- +ACo- Implemented recalc+AF8-rate +AD4- +AD4- Changes v1 -+AD4- v2: +AD4- +ACo- Renamed folder to axs10x (as suggested by Alexey Brodkin) +AD4- +ACo- Added more supported rates +AFs-snip+AF0- +AD4- diff --git a/Documentation/devicetree/bindings/clock/i2s-pll-clock.txt b/Documentation/devicetree/bindings/clock/i2s- +AD4- pll-clock.txt +AD4- new file mode 100644 +AD4- index 0000000..ff86a41 +AD4- --- /dev/null +AD4- +-+-+- b/Documentation/devicetree/bindings/clock/i2s-pll-clock.txt +AD4- +AEAAQA- -0,0 +-1,17 +AEAAQA- +AD4- +-Binding for the AXS10X I2S PLL clock +AD4- +- +AD4- +-This binding uses the common clock binding+AFs-1+AF0-. +AD4- +- +AD4- +-+AFs-1+AF0- Documentation/devicetree/bindings/clock/clock-bindings.txt +AD4- +- +AD4- +-Required properties: +AD4- +-- compatible: shall be +ACI-snps,i2s-pll-clock+ACI- +AD4- +-- +ACM-clock-cells: from common clock binding+ADs- Should always be set to 0. +AD4- +-- reg : Address and length of the I2S PLL register set. +AD4- +- +AD4- +-Example: +AD4- +- clock+AEA-0x100a0 +AHs- Please remove +ACI-0x+ACI- from node name. +AD4- +- compatible +AD0- +ACI-snps,i2s-pll-clock+ACIAOw- +AD4- +- reg +AD0- +ADw-0x100a0 0x10+AD4AOw- +AD4- +- +ACM-clock-cells +AD0- +ADw-0+AD4AOw- +AD4- +- +AH0AOw- +AD4- diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile +AD4- index 46869d6..2ca62dc6 100644 +AD4- --- a/drivers/clk/Makefile +AD4- +-+-+- b/drivers/clk/Makefile +AD4- +AEAAQA- -84,3 +-84,4 +AEAAQA- obj-+ACQ-(CONFIG+AF8-X86) +-+AD0- x86/ +AD4- +AKA-obj-+ACQ-(CONFIG+AF8-ARCH+AF8-ZX) +-+AD0- zte/ +AD4- +AKA-obj-+ACQ-(CONFIG+AF8-ARCH+AF8-ZYNQ) +-+AD0- zynq/ +AD4- +AKA-obj-+ACQ-(CONFIG+AF8-H8300) +-+AD0- h8300/ +AD4- +-obj-+ACQ-(CONFIG+AF8-ARC+AF8-PLAT+AF8-AXS10X) +-+AD0- axs10x/ +AD4- diff --git a/drivers/clk/axs10x/Makefile b/drivers/clk/axs10x/Makefile +AD4- new file mode 100644 +AD4- index 0000000..01996b8 +AD4- --- /dev/null +AD4- +-+-+- b/drivers/clk/axs10x/Makefile +AD4- +AEAAQA- -0,0 +-1 +AEAAQA- +AD4- +-obj-y +-+AD0- i2s+AF8-pll+AF8-clock.o +AD4- diff --git a/drivers/clk/axs10x/i2s+AF8-pll+AF8-clock.c b/drivers/clk/axs10x/i2s+AF8-pll+AF8-clock.c +AD4- new file mode 100644 +AD4- index 0000000..3ba4e2f +AD4- --- /dev/null +AD4- +-+-+- b/drivers/clk/axs10x/i2s+AF8-pll+AF8-clock.c +AD4- +AEAAQA- -0,0 +-1,217 +AEAAQA- +AD4- +-/+ACo- +AD4- +- +ACo- Synopsys AXS10X SDP I2S PLL clock driver +AD4- +- +ACo- +AD4- +- +ACo- Copyright (C) 2016 Synopsys +AD4- +- +ACo- +AD4- +- +ACo- This file is licensed under the terms of the GNU General Public +AD4- +- +ACo- License version 2. This program is licensed +ACI-as is+ACI- without any +AD4- +- +ACo- warranty of any kind, whether express or implied. +AD4- +- +ACo-/ +AD4- +- +AD4- +-+ACM-include +ADw-linux/platform+AF8-device.h+AD4- +AD4- +-+ACM-include +ADw-linux/module.h+AD4- +AD4- +-+ACM-include +ADw-linux/clk-provider.h+AD4- +AD4- +-+ACM-include +ADw-linux/err.h+AD4- +AD4- +-+ACM-include +ADw-linux/device.h+AD4- +ACI-linux/platform+AF8-device.h+ACI- includes +ACI-linux/device.h+ACI- so you may make this list of headers a little bit shorter. +AD4- +-+ACM-include +ADw-linux/of+AF8-address.h+AD4- +AD4- +-+ACM-include +ADw-linux/slab.h+AD4- +AD4- +-+ACM-include +ADw-linux/of.h+AD4- +ACI-linux/of+AF8-address.h+ACI- already includes +ACI-linux/of.h+ACI-. +AFs-snip+AF0- +AD4- +- +AD4- +-static const struct of+AF8-device+AF8-id i2s+AF8-pll+AF8-clk+AF8-id+AFsAXQ- +AD0- +AHs- +AD4- +- +AHs- .compatible +AD0- +ACI-snps,i2s-pll-clock+ACI-, +AH0-, I would think that it makes sense to add the board name in this compatible string. So something like+AKAAIg-snps,axs10x-i2s-pll-clock+ACI- IMHO looks much more informative. Also adding Rob Herring and DT mailing list in Cc. Please make sure Rod acks your bindings and corresponding docs. -Alexey-- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753163AbcDKQsD (ORCPT ); Mon, 11 Apr 2016 12:48:03 -0400 Received: from us01smtprelay-2.synopsys.com ([198.182.60.111]:53109 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751175AbcDKQsA convert rfc822-to-8bit (ORCPT ); Mon, 11 Apr 2016 12:48:00 -0400 From: Alexey Brodkin To: Jose Abreu CC: "linux-kernel@vger.kernel.org" , "robh+dt@kernel.org" , "mturquette@baylibre.com" , Carlos Palminha , "devicetree@vger.kernel.org" , "linux-snps-arc@lists.infradead.org" , Vineet Gupta , "linux-clk@vger.kernel.org" , "sboyd@codeaurora.org" Subject: Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver Thread-Topic: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver Thread-Index: AQHRlBHjJ0YWHd1XD02mGCQKfTDzGQ== Date: Mon, 11 Apr 2016 16:47:51 +0000 Message-ID: <1460393270.5119.20.camel@synopsys.com> References: <50c75be8ecab225a1dd49628a173d211a02755b2.1459791946.git.joabreu@synopsys.com> In-Reply-To: <50c75be8ecab225a1dd49628a173d211a02755b2.1459791946.git.joabreu@synopsys.com> Accept-Language: en-US, ru-RU Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.9.129.131] Content-Type: text/plain; charset="utf-7" Content-ID: <326FDFAA055727429000EC50BBEA85FF@internal.synopsys.com> Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jose, On Mon, 2016-04-11 at 11:41 +-0100, Jose Abreu wrote: +AD4- The ARC SDP I2S clock can be programmed using a +AD4- specific PLL. +AD4- +AD4- This patch has the goal of adding a clock driver +AD4- that programs this PLL. +AD4- +AD4- At this moment the rate values are hardcoded in +AD4- a table but in the future it would be ideal to +AD4- use a function which determines the PLL values +AD4- given the desired rate. +AD4- +AD4- Signed-off-by: Jose Abreu +ADw-joabreu+AEA-synopsys.com+AD4- +AD4- --- +AD4- +AD4- Changes v3 -+AD4- v4: +AD4- +ACo- Added binding document (as suggested by Stephen Boyd) +AD4- +ACo- Minor code style fixes (as suggested by Stephen Boyd) +AD4- +ACo- Use ioremap (as suggested by Stephen Boyd) +AD4- +ACo- Implement round+AF8-rate (as suggested by Stephen Boyd) +AD4- +ACo- Change to platform driver (as suggested by Stephen Boyd) +AD4- +ACo- Use +AHs-readl/writel+AH0AXw-relaxed (as suggested by Vineet Gupta) +AD4- +AD4- Changes v2 -+AD4- v3: +AD4- +ACo- Implemented recalc+AF8-rate +AD4- +AD4- Changes v1 -+AD4- v2: +AD4- +ACo- Renamed folder to axs10x (as suggested by Alexey Brodkin) +AD4- +ACo- Added more supported rates +AFs-snip+AF0- +AD4- diff --git a/Documentation/devicetree/bindings/clock/i2s-pll-clock.txt b/Documentation/devicetree/bindings/clock/i2s- +AD4- pll-clock.txt +AD4- new file mode 100644 +AD4- index 0000000..ff86a41 +AD4- --- /dev/null +AD4- +-+-+- b/Documentation/devicetree/bindings/clock/i2s-pll-clock.txt +AD4- +AEAAQA- -0,0 +-1,17 +AEAAQA- +AD4- +-Binding for the AXS10X I2S PLL clock +AD4- +- +AD4- +-This binding uses the common clock binding+AFs-1+AF0-. +AD4- +- +AD4- +-+AFs-1+AF0- Documentation/devicetree/bindings/clock/clock-bindings.txt +AD4- +- +AD4- +-Required properties: +AD4- +-- compatible: shall be +ACI-snps,i2s-pll-clock+ACI- +AD4- +-- +ACM-clock-cells: from common clock binding+ADs- Should always be set to 0. +AD4- +-- reg : Address and length of the I2S PLL register set. +AD4- +- +AD4- +-Example: +AD4- +- clock+AEA-0x100a0 +AHs- Please remove +ACI-0x+ACI- from node name. +AD4- +- compatible +AD0- +ACI-snps,i2s-pll-clock+ACIAOw- +AD4- +- reg +AD0- +ADw-0x100a0 0x10+AD4AOw- +AD4- +- +ACM-clock-cells +AD0- +ADw-0+AD4AOw- +AD4- +- +AH0AOw- +AD4- diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile +AD4- index 46869d6..2ca62dc6 100644 +AD4- --- a/drivers/clk/Makefile +AD4- +-+-+- b/drivers/clk/Makefile +AD4- +AEAAQA- -84,3 +-84,4 +AEAAQA- obj-+ACQ-(CONFIG+AF8-X86) +-+AD0- x86/ +AD4- +AKA-obj-+ACQ-(CONFIG+AF8-ARCH+AF8-ZX) +-+AD0- zte/ +AD4- +AKA-obj-+ACQ-(CONFIG+AF8-ARCH+AF8-ZYNQ) +-+AD0- zynq/ +AD4- +AKA-obj-+ACQ-(CONFIG+AF8-H8300) +-+AD0- h8300/ +AD4- +-obj-+ACQ-(CONFIG+AF8-ARC+AF8-PLAT+AF8-AXS10X) +-+AD0- axs10x/ +AD4- diff --git a/drivers/clk/axs10x/Makefile b/drivers/clk/axs10x/Makefile +AD4- new file mode 100644 +AD4- index 0000000..01996b8 +AD4- --- /dev/null +AD4- +-+-+- b/drivers/clk/axs10x/Makefile +AD4- +AEAAQA- -0,0 +-1 +AEAAQA- +AD4- +-obj-y +-+AD0- i2s+AF8-pll+AF8-clock.o +AD4- diff --git a/drivers/clk/axs10x/i2s+AF8-pll+AF8-clock.c b/drivers/clk/axs10x/i2s+AF8-pll+AF8-clock.c +AD4- new file mode 100644 +AD4- index 0000000..3ba4e2f +AD4- --- /dev/null +AD4- +-+-+- b/drivers/clk/axs10x/i2s+AF8-pll+AF8-clock.c +AD4- +AEAAQA- -0,0 +-1,217 +AEAAQA- +AD4- +-/+ACo- +AD4- +- +ACo- Synopsys AXS10X SDP I2S PLL clock driver +AD4- +- +ACo- +AD4- +- +ACo- Copyright (C) 2016 Synopsys +AD4- +- +ACo- +AD4- +- +ACo- This file is licensed under the terms of the GNU General Public +AD4- +- +ACo- License version 2. This program is licensed +ACI-as is+ACI- without any +AD4- +- +ACo- warranty of any kind, whether express or implied. +AD4- +- +ACo-/ +AD4- +- +AD4- +-+ACM-include +ADw-linux/platform+AF8-device.h+AD4- +AD4- +-+ACM-include +ADw-linux/module.h+AD4- +AD4- +-+ACM-include +ADw-linux/clk-provider.h+AD4- +AD4- +-+ACM-include +ADw-linux/err.h+AD4- +AD4- +-+ACM-include +ADw-linux/device.h+AD4- +ACI-linux/platform+AF8-device.h+ACI- includes +ACI-linux/device.h+ACI- so you may make this list of headers a little bit shorter. +AD4- +-+ACM-include +ADw-linux/of+AF8-address.h+AD4- +AD4- +-+ACM-include +ADw-linux/slab.h+AD4- +AD4- +-+ACM-include +ADw-linux/of.h+AD4- +ACI-linux/of+AF8-address.h+ACI- already includes +ACI-linux/of.h+ACI-. +AFs-snip+AF0- +AD4- +- +AD4- +-static const struct of+AF8-device+AF8-id i2s+AF8-pll+AF8-clk+AF8-id+AFsAXQ- +AD0- +AHs- +AD4- +- +AHs- .compatible +AD0- +ACI-snps,i2s-pll-clock+ACI-, +AH0-, I would think that it makes sense to add the board name in this compatible string. So something like+AKAAIg-snps,axs10x-i2s-pll-clock+ACI- IMHO looks much more informative. Also adding Rob Herring and DT mailing list in Cc. Please make sure Rod acks your bindings and corresponding docs. -Alexey