diff for duplicates of <14610453.rKm3MBREMz@diego> diff --git a/a/content_digest b/N1/content_digest index 2433284..b930123 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -36,7 +36,11 @@ arnd@arndb.de fabio.estevam@nxp.com zhangqing@rock-chips.com - " kever.yang@rock-chips.com\0" + kever.yang@rock-chips.com + tony.xie@rock-chips.com + huangtao@rock-chips.com + yhx@rock-chips.com + " rocky.hao@rock-chips.com\0" "\00:1\0" "b\0" "Hi,\n" @@ -544,4 +548,4 @@ "\n" Heiko -4d9eca2733aaa3fb3f9d019caf3447e86ff7b658ac1d461d720f4c66e5bd4a95 +fdc000d225f55eda27da34bc925b93b1a24733c6dc1e7d4ccc249b6fe61557ac
diff --git a/a/1.txt b/N2/1.txt index 584629f..e320476 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,6 +1,6 @@ Hi, -Am Donnerstag, 16. März 2017, 21:17:22 CET schrieb cl@rock-chips.com: +Am Donnerstag, 16. M?rz 2017, 21:17:22 CET schrieb cl at rock-chips.com: > From: Liang Chen <cl@rock-chips.com> > > This patch adds core dtsi file for Rockchip RK3328 SoCs. @@ -91,26 +91,26 @@ Am Donnerstag, 16. März 2017, 21:17:22 CET schrieb cl@rock-chips.com: > + #size-cells = <0>; > + -> + cpu0: cpu@0 { +> + cpu0: cpu at 0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + clocks = <&cru ARMCLK>; > + }; -> + cpu1: cpu@1 { +> + cpu1: cpu at 1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + }; -> + cpu2: cpu@2 { +> + cpu2: cpu at 2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x2>; > + enable-method = "psci"; > + }; -> + cpu3: cpu@3 { +> + cpu3: cpu at 3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x3>; @@ -154,7 +154,7 @@ IRQ_TYPE_LEVEL_LOW)>, [...] -> + wdt: watchdog@ff1a0000 { +> + wdt: watchdog at ff1a0000 { > + compatible = "snps,dw-wdt"; > + reg = <0x0 0xff1a0000 0x0 0x100>; > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; @@ -170,7 +170,7 @@ amba block above arm-pmu please > + #size-cells = <2>; > + ranges; > + -> + dmac: dmac@ff1f0000 { +> + dmac: dmac at ff1f0000 { > + compatible = "arm,pl330", "arm,primecell"; > + reg = <0x0 0xff1f0000 0x0 0x4000>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, @@ -181,7 +181,7 @@ amba block above arm-pmu please > + }; > + }; > + -> + saradc: saradc@ff280000 { +> + saradc: saradc at ff280000 { > + compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; > + reg = <0x0 0xff280000 0x0 0x100>; > + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; @@ -193,7 +193,7 @@ amba block above arm-pmu please > + status = "disabled"; > + }; > + -> + cru: clock-controller@ff440000 { +> + cru: clock-controller at ff440000 { > + compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; > + reg = <0x0 0xff440000 0x0 0x1000>; > + rockchip,grf = <&grf>; @@ -267,10 +267,10 @@ The cru assigned clocks are really only for system-wide shared clocks. > + <32768>, <32768>; > + }; > + -> + gmac2io: eth@ff540000 { +> + gmac2io: eth at ff540000 { phandle should be gmac instead? -Node name, ethernet@ff540000 +Node name, ethernet at ff540000 > + compatible = "rockchip,rk3328-gmac"; > + reg = <0x0 0xff540000 0x0 0x10000>; @@ -290,7 +290,7 @@ Node name, ethernet@ff540000 > + status = "disabled"; > + }; > + -> + gic: interrupt-controller@ff811000 { +> + gic: interrupt-controller at ff811000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + #address-cells = <0>; @@ -310,7 +310,7 @@ Node name, ethernet@ff540000 > + #size-cells = <2>; > + ranges; > + -> + gpio0: gpio0@ff210000 { +> + gpio0: gpio0 at ff210000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x0 0xff210000 0x0 0x100>; > + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; @@ -323,7 +323,7 @@ Node name, ethernet@ff540000 > + #interrupt-cells = <2>; > + }; > + -> + gpio1: gpio1@ff220000 { +> + gpio1: gpio1 at ff220000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x0 0xff220000 0x0 0x100>; > + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; @@ -336,7 +336,7 @@ Node name, ethernet@ff540000 > + #interrupt-cells = <2>; > + }; > + -> + gpio2: gpio2@ff230000 { +> + gpio2: gpio2 at ff230000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x0 0xff230000 0x0 0x100>; > + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; @@ -349,7 +349,7 @@ Node name, ethernet@ff540000 > + #interrupt-cells = <2>; > + }; > + -> + gpio3: gpio3@ff240000 { +> + gpio3: gpio3 at ff240000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x0 0xff240000 0x0 0x100>; > + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; diff --git a/a/content_digest b/N2/content_digest index 2433284..7c197da 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,47 +1,14 @@ "ref\01489670244-13328-1-git-send-email-cl@rock-chips.com\0" "ref\01489670244-13328-5-git-send-email-cl@rock-chips.com\0" - "From\0Heiko St\303\274bner <heiko@sntech.de>\0" - "Subject\0Re: [PATCH v2 4/6] arm64: dts: rockchip: add core dtsi file for RK3328 SoCs\0" + "From\0heiko@sntech.de (Heiko St\303\274bner)\0" + "Subject\0[PATCH v2 4/6] arm64: dts: rockchip: add core dtsi file for RK3328 SoCs\0" "Date\0Tue, 21 Mar 2017 09:55:56 +0100\0" - "To\0cl@rock-chips.com\0" - "Cc\0robh+dt@kernel.org" - mark.rutland@arm.com - zhengxing@rock-chips.com - andy.yan@rock-chips.com - jay.xu@rock-chips.com - matthias.bgg@gmail.com - paweljarosz3691@gmail.com - devicetree@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-rockchip@lists.infradead.org - linux-kernel@vger.kernel.org - wsa@the-dreams.de - linux-i2c@vger.kernel.org - jic23@kernel.org - knaack.h@gmx.de - lars@metafoo.de - pmeerw@pmeerw.net - wxt@rock-chips.com - david.wu@rock-chips.com - linux-iio@vger.kernel.org - shawn.lin@rock-chips.com - akpm@linux-foundation.org - dianders@chromium.org - yamada.masahiro@socionext.com - catalin.marinas@arm.com - will.deacon@arm.com - afaerber@suse.de - shawnguo@kernel.org - khilman@baylibre.com - arnd@arndb.de - fabio.estevam@nxp.com - zhangqing@rock-chips.com - " kever.yang@rock-chips.com\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi,\n" "\n" - "Am Donnerstag, 16. M\303\244rz 2017, 21:17:22 CET schrieb cl@rock-chips.com:\n" + "Am Donnerstag, 16. M?rz 2017, 21:17:22 CET schrieb cl at rock-chips.com:\n" "> From: Liang Chen <cl@rock-chips.com>\n" "> \n" "> This patch adds core dtsi file for Rockchip RK3328 SoCs.\n" @@ -132,26 +99,26 @@ "\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu0: cpu@0 {\n" + "> +\t\tcpu0: cpu at 0 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x0>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t\tclocks = <&cru ARMCLK>;\n" "> +\t\t};\n" - "> +\t\tcpu1: cpu@1 {\n" + "> +\t\tcpu1: cpu at 1 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x1>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" - "> +\t\tcpu2: cpu@2 {\n" + "> +\t\tcpu2: cpu at 2 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x2>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" - "> +\t\tcpu3: cpu@3 {\n" + "> +\t\tcpu3: cpu at 3 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x3>;\n" @@ -195,7 +162,7 @@ "\n" "[...]\n" "\n" - "> +\twdt: watchdog@ff1a0000 {\n" + "> +\twdt: watchdog at ff1a0000 {\n" "> +\t\tcompatible = \"snps,dw-wdt\";\n" "> +\t\treg = <0x0 0xff1a0000 0x0 0x100>;\n" "> +\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -211,7 +178,7 @@ "> +\t\t#size-cells = <2>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tdmac: dmac@ff1f0000 {\n" + "> +\t\tdmac: dmac at ff1f0000 {\n" "> +\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n" "> +\t\t\treg = <0x0 0xff1f0000 0x0 0x4000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -222,7 +189,7 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tsaradc: saradc@ff280000 {\n" + "> +\tsaradc: saradc at ff280000 {\n" "> +\t\tcompatible = \"rockchip,rk3328-saradc\", \"rockchip,rk3399-saradc\";\n" "> +\t\treg = <0x0 0xff280000 0x0 0x100>;\n" "> +\t\tinterrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -234,7 +201,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tcru: clock-controller@ff440000 {\n" + "> +\tcru: clock-controller at ff440000 {\n" "> +\t\tcompatible = \"rockchip,rk3328-cru\", \"rockchip,cru\", \"syscon\";\n" "> +\t\treg = <0x0 0xff440000 0x0 0x1000>;\n" "> +\t\trockchip,grf = <&grf>;\n" @@ -308,10 +275,10 @@ "> +\t\t\t<32768>, <32768>;\n" "> +\t};\n" "> +\n" - "> +\tgmac2io: eth@ff540000 {\n" + "> +\tgmac2io: eth at ff540000 {\n" "\n" "phandle should be gmac instead?\n" - "Node name, ethernet@ff540000\n" + "Node name, ethernet at ff540000\n" "\n" "> +\t\tcompatible = \"rockchip,rk3328-gmac\";\n" "> +\t\treg = <0x0 0xff540000 0x0 0x10000>;\n" @@ -331,7 +298,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller@ff811000 {\n" + "> +\tgic: interrupt-controller at ff811000 {\n" "> +\t\tcompatible = \"arm,gic-400\";\n" "> +\t\t#interrupt-cells = <3>;\n" "> +\t\t#address-cells = <0>;\n" @@ -351,7 +318,7 @@ "> +\t\t#size-cells = <2>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tgpio0: gpio0@ff210000 {\n" + "> +\t\tgpio0: gpio0 at ff210000 {\n" "> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "> +\t\t\treg = <0x0 0xff210000 0x0 0x100>;\n" "> +\t\t\tinterrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -364,7 +331,7 @@ "> +\t\t\t#interrupt-cells = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio1: gpio1@ff220000 {\n" + "> +\t\tgpio1: gpio1 at ff220000 {\n" "> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "> +\t\t\treg = <0x0 0xff220000 0x0 0x100>;\n" "> +\t\t\tinterrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -377,7 +344,7 @@ "> +\t\t\t#interrupt-cells = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio2: gpio2@ff230000 {\n" + "> +\t\tgpio2: gpio2 at ff230000 {\n" "> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "> +\t\t\treg = <0x0 0xff230000 0x0 0x100>;\n" "> +\t\t\tinterrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -390,7 +357,7 @@ "> +\t\t\t#interrupt-cells = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio3: gpio3@ff240000 {\n" + "> +\t\tgpio3: gpio3 at ff240000 {\n" "> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "> +\t\t\treg = <0x0 0xff240000 0x0 0x100>;\n" "> +\t\t\tinterrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -544,4 +511,4 @@ "\n" Heiko -4d9eca2733aaa3fb3f9d019caf3447e86ff7b658ac1d461d720f4c66e5bd4a95 +b547b37f038915d5879bc5615f35abbf85bae5540e43caf2674aa4f43af34926
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