diff for duplicates of <1461168765.3149.31.camel@synopsys.com> diff --git a/a/1.txt b/N1/1.txt index 357cfb5..31ef511 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,6 +1,6 @@ Hi Jose, Stephen, -On Wed, 2016-04-20 at 10:47 +0100, Jose Abreu wrote: +On Wed, 2016-04-20@10:47 +0100, Jose Abreu wrote: > Hi Stephen, > > @@ -34,16 +34,16 @@ Read my comment below. > > properly express the clk tree. > > > Can I use a property in the DT to pass this reference clock? something like this: -> snps,parent-freq = <0xFBED9 27000000>, <0x0 28224000>; /* Tuple +> ????snps,parent-freq = <0xFBED9 27000000>, <0x0 28224000>; /* Tuple > <fpga-version reference-clock-freq>, fpga-version = 0 is default */ > > Or use a parent clock? like: -> clk { -> compatible = "fixed-clock"; -> clock-frequency = <27000000>; -> #clock-cells = <0>; -> snps,fpga-version = <0xFBED9>; -> } +> ????clk { +> ????????compatible = "fixed-clock"; +> ????????clock-frequency = <27000000>; +> ????????#clock-cells = <0>; +> ????????snps,fpga-version = <0xFBED9>; +> ????} > > It is important to distinguish between the different versions automatically, is > any of these solutions ok? @@ -65,16 +65,16 @@ And in the driver itself value of that master clock will be used for population of "pll_clk->ref_clk" directly. These are benefits we'll get with that approach: - [1] We escape any IOs not related to our clock device (I mean - "snps,i2s-pll-clock") itself. - [2] We'll use whatever reference clock value is given. - I.e. we'll be able to do a fix-up of that reference clock - value early in platform code depending on HW we're running on. - That's what people do here and there. - [3] Remember another clock driver for AXS10x board is right around - the corner. I mean the one for ARC PGU which uses exactly the same - master clock. So one fixup as mentioned above will work - at once for 2 clock drivers. +?[1] We escape any IOs not related to our clock device (I mean +? ? ?"snps,i2s-pll-clock") itself. +?[2] We'll use whatever reference clock value is given. +? ? ?I.e. we'll be able to do a fix-up of that reference clock +? ? ?value early in platform code depending on HW we're running on. +? ? ?That's what people do here and there. +?[3] Remember another clock driver for AXS10x board is right around +? ? ?the corner. I mean the one for ARC PGU which uses exactly the same +? ? ?master clock. So one fixup as mentioned above will work +? ? ?at once for 2 clock drivers. Let me know if above makes sense. diff --git a/a/content_digest b/N1/content_digest index af80aac..456df10 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -5,21 +5,15 @@ "ref\05715F6AC.7090501@synopsys.com\0" "ref\020160420015451.GH15324@codeaurora.org\0" "ref\05717503F.7020806@synopsys.com\0" - "From\0Alexey Brodkin <Alexey.Brodkin@synopsys.com>\0" - "Subject\0Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver\0" + "From\0Alexey.Brodkin@synopsys.com (Alexey Brodkin)\0" + "Subject\0[RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver\0" "Date\0Wed, 20 Apr 2016 16:12:50 +0000\0" - "To\0sboyd@codeaurora.org <sboyd@codeaurora.org>" - " Jose Abreu <Jose.Abreu@synopsys.com>\0" - "Cc\0Carlos Palminha <CARLOS.PALMINHA@synopsys.com>" - linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> - Vineet Gupta <Vineet.Gupta1@synopsys.com> - linux-clk@vger.kernel.org <linux-clk@vger.kernel.org> - " linux-snps-arc@lists.infradead.org <linux-snps-arc@lists.infradead.org>\0" + "To\0linux-snps-arc@lists.infradead.org\0" "\00:1\0" "b\0" "Hi Jose, Stephen,\n" "\n" - "On Wed, 2016-04-20 at 10:47 +0100, Jose Abreu wrote:\n" + "On Wed, 2016-04-20@10:47 +0100, Jose Abreu wrote:\n" "> Hi Stephen,\n" "> \n" "> \n" @@ -53,16 +47,16 @@ "> > properly express the clk tree.\n" "> > \n" "> Can I use a property in the DT to pass this reference clock? something like this:\n" - "> \302\240\302\240\302\240\302\240snps,parent-freq = <0xFBED9 27000000>, <0x0 28224000>; /* Tuple\n" + "> ????snps,parent-freq = <0xFBED9 27000000>, <0x0 28224000>; /* Tuple\n" "> <fpga-version reference-clock-freq>, fpga-version = 0 is default */\n" "> \n" "> Or use a parent clock? like:\n" - "> \302\240\302\240\302\240\302\240clk {\n" - "> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240compatible = \"fixed-clock\";\n" - "> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240clock-frequency = <27000000>;\n" - "> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240#clock-cells = <0>;\n" - "> \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240snps,fpga-version = <0xFBED9>;\n" - "> \302\240\302\240\302\240\302\240}\n" + "> ????clk {\n" + "> ????????compatible = \"fixed-clock\";\n" + "> ????????clock-frequency = <27000000>;\n" + "> ????????#clock-cells = <0>;\n" + "> ????????snps,fpga-version = <0xFBED9>;\n" + "> ????}\n" "> \n" "> It is important to distinguish between the different versions automatically, is\n" "> any of these solutions ok?\n" @@ -84,19 +78,19 @@ "population of \"pll_clk->ref_clk\" directly.\n" "\n" "These are benefits we'll get with that approach:\n" - "\302\240[1] We escape any IOs not related to our clock device (I mean\n" - "\302\240 \302\240 \302\240\"snps,i2s-pll-clock\") itself.\n" - "\302\240[2] We'll use whatever reference clock value is given.\n" - "\302\240 \302\240 \302\240I.e. we'll be able to do a fix-up of that reference clock\n" - "\302\240 \302\240 \302\240value early in platform code depending on HW we're running on.\n" - "\302\240 \302\240 \302\240That's what people do here and there.\n" - "\302\240[3] Remember another clock driver for AXS10x board is right around\n" - "\302\240 \302\240 \302\240the corner. I mean the one for ARC PGU which uses exactly the same\n" - "\302\240 \302\240 \302\240master clock. So one fixup as mentioned above will work\n" - "\302\240 \302\240 \302\240at once for 2 clock drivers.\n" + "?[1] We escape any IOs not related to our clock device (I mean\n" + "? ? ?\"snps,i2s-pll-clock\") itself.\n" + "?[2] We'll use whatever reference clock value is given.\n" + "? ? ?I.e. we'll be able to do a fix-up of that reference clock\n" + "? ? ?value early in platform code depending on HW we're running on.\n" + "? ? ?That's what people do here and there.\n" + "?[3] Remember another clock driver for AXS10x board is right around\n" + "? ? ?the corner. I mean the one for ARC PGU which uses exactly the same\n" + "? ? ?master clock. So one fixup as mentioned above will work\n" + "? ? ?at once for 2 clock drivers.\n" "\n" "Let me know if above makes sense.\n" "\n" -Alexey -1e46b1623aaf93d743790c28cf51203cec6c0c5995787be35f13e916d16b6f3d +7507d8b766684e0e3e021b033fc8c993384592fb5c7b4cfe83ed41b9627c46a7
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