diff for duplicates of <1461241114.2928.4.camel@synopsys.com> diff --git a/a/1.txt b/N1/1.txt index ea4d660..1f2eae6 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,6 +1,6 @@ Hi Jose, -On Thu, 2016-04-21 at 10:51 +0100, Jose Abreu wrote: +On Thu, 2016-04-21@10:51 +0100, Jose Abreu wrote: > Hi Alexey, @@ -14,16 +14,16 @@ On Thu, 2016-04-21 at 10:51 +0100, Jose Abreu wrote: > > > > properly express the clk tree. > > > > > > > Can I use a property in the DT to pass this reference clock? something like this: -> > > snps,parent-freq = <0xFBED9 27000000>, <0x0 28224000>; /* Tuple +> > > ????snps,parent-freq = <0xFBED9 27000000>, <0x0 28224000>; /* Tuple > > > <fpga-version reference-clock-freq>, fpga-version = 0 is default */ > > > > > > Or use a parent clock? like: -> > > clk { -> > > compatible = "fixed-clock"; -> > > clock-frequency = <27000000>; -> > > #clock-cells = <0>; -> > > snps,fpga-version = <0xFBED9>; -> > > } +> > > ????clk { +> > > ????????compatible = "fixed-clock"; +> > > ????????clock-frequency = <27000000>; +> > > ????????#clock-cells = <0>; +> > > ????????snps,fpga-version = <0xFBED9>; +> > > ????} > > > > > > It is important to distinguish between the different versions automatically, is > > > any of these solutions ok? @@ -44,20 +44,20 @@ On Thu, 2016-04-21 at 10:51 +0100, Jose Abreu wrote: > > population of "pll_clk->ref_clk" directly. > > > > These are benefits we'll get with that approach: -> > [1] We escape any IOs not related to our clock device (I mean -> > "snps,i2s-pll-clock") itself. -> > [2] We'll use whatever reference clock value is given. -> > I.e. we'll be able to do a fix-up of that reference clock -> > value early in platform code depending on HW we're running on. -> > That's what people do here and there. -> > [3] Remember another clock driver for AXS10x board is right around -> > the corner. I mean the one for ARC PGU which uses exactly the same -> > master clock. So one fixup as mentioned above will work -> > at once for 2 clock drivers. +> > ?[1] We escape any IOs not related to our clock device (I mean +> > ?????"snps,i2s-pll-clock") itself. +> > ?[2] We'll use whatever reference clock value is given. +> > ?????I.e. we'll be able to do a fix-up of that reference clock +> > ?????value early in platform code depending on HW we're running on. +> > ?????That's what people do here and there. +> > ?[3] Remember another clock driver for AXS10x board is right around +> > ?????the corner. I mean the one for ARC PGU which uses exactly the same +> > ?????master clock. So one fixup as mentioned above will work +> > ?????at once for 2 clock drivers. > > > > Let me know if above makes sense. > That approach can't be used because the reference clock value will change in the -> next firmware release. The new release will have a reference clock of 28224000 +> next firmware release.??The new release will have a reference clock of 28224000 > Hz instead of the usual 27000000 Hz, so we need to have a way to distinguish > between them. Because of that we can't have only one master clock unless you > state to users that they have to change the reference clock value when using the @@ -68,7 +68,7 @@ On Thu, 2016-04-21 at 10:51 +0100, Jose Abreu wrote: Ok reference clock will change. But I may guess we'll still be able to determine at least that new firmware version in run-time, right? If so we'll update a fix-up in -early axs10x platform code so that reference clock will be set as 28224000 Hz. +early axs10x platform code so that reference clock will be set as?28224000 Hz. And indeed 2 DT files is a no go - we want to run the same one binary (with built-in .dtb) on all flavors of AXS boards. And fix-up I'm talking about diff --git a/a/content_digest b/N1/content_digest index a07a33f..3357db5 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -7,21 +7,15 @@ "ref\05717503F.7020806@synopsys.com\0" "ref\01461168765.3149.31.camel@synopsys.com\0" "ref\05718A298.50601@synopsys.com\0" - "From\0Alexey Brodkin <Alexey.Brodkin@synopsys.com>\0" - "Subject\0Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver\0" + "From\0Alexey.Brodkin@synopsys.com (Alexey Brodkin)\0" + "Subject\0[RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver\0" "Date\0Thu, 21 Apr 2016 12:18:39 +0000\0" - "To\0sboyd@codeaurora.org <sboyd@codeaurora.org>" - " Jose Abreu <Jose.Abreu@synopsys.com>\0" - "Cc\0Carlos Palminha <CARLOS.PALMINHA@synopsys.com>" - linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> - Vineet Gupta <Vineet.Gupta1@synopsys.com> - linux-clk@vger.kernel.org <linux-clk@vger.kernel.org> - " linux-snps-arc@lists.infradead.org <linux-snps-arc@lists.infradead.org>\0" + "To\0linux-snps-arc@lists.infradead.org\0" "\00:1\0" "b\0" "Hi Jose,\n" "\n" - "On Thu, 2016-04-21 at 10:51 +0100, Jose Abreu wrote:\n" + "On Thu, 2016-04-21@10:51 +0100, Jose Abreu wrote:\n" "> Hi Alexey,\n" "\n" "\n" @@ -35,16 +29,16 @@ "> > > > properly express the clk tree.\n" "> > > > \n" "> > > Can I use a property in the DT to pass this reference clock? something like this:\n" - "> > > \302\240\302\240\302\240\302\240snps,parent-freq = <0xFBED9 27000000>, <0x0 28224000>; /* Tuple\n" + "> > > ????snps,parent-freq = <0xFBED9 27000000>, <0x0 28224000>; /* Tuple\n" "> > > <fpga-version reference-clock-freq>, fpga-version = 0 is default */\n" "> > > \n" "> > > Or use a parent clock? like:\n" - "> > > \302\240\302\240\302\240\302\240clk {\n" - "> > > \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240compatible = \"fixed-clock\";\n" - "> > > \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240clock-frequency = <27000000>;\n" - "> > > \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240#clock-cells = <0>;\n" - "> > > \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240snps,fpga-version = <0xFBED9>;\n" - "> > > \302\240\302\240\302\240\302\240}\n" + "> > > ????clk {\n" + "> > > ????????compatible = \"fixed-clock\";\n" + "> > > ????????clock-frequency = <27000000>;\n" + "> > > ????????#clock-cells = <0>;\n" + "> > > ????????snps,fpga-version = <0xFBED9>;\n" + "> > > ????}\n" "> > > \n" "> > > It is important to distinguish between the different versions automatically, is\n" "> > > any of these solutions ok?\n" @@ -65,20 +59,20 @@ "> > population of \"pll_clk->ref_clk\" directly.\n" "> > \n" "> > These are benefits we'll get with that approach:\n" - "> > \302\240[1] We escape any IOs not related to our clock device (I mean\n" - "> > \302\240\302\240\302\240\302\240\302\240\"snps,i2s-pll-clock\") itself.\n" - "> > \302\240[2] We'll use whatever reference clock value is given.\n" - "> > \302\240\302\240\302\240\302\240\302\240I.e. we'll be able to do a fix-up of that reference clock\n" - "> > \302\240\302\240\302\240\302\240\302\240value early in platform code depending on HW we're running on.\n" - "> > \302\240\302\240\302\240\302\240\302\240That's what people do here and there.\n" - "> > \302\240[3] Remember another clock driver for AXS10x board is right around\n" - "> > \302\240\302\240\302\240\302\240\302\240the corner. I mean the one for ARC PGU which uses exactly the same\n" - "> > \302\240\302\240\302\240\302\240\302\240master clock. So one fixup as mentioned above will work\n" - "> > \302\240\302\240\302\240\302\240\302\240at once for 2 clock drivers.\n" + "> > ?[1] We escape any IOs not related to our clock device (I mean\n" + "> > ?????\"snps,i2s-pll-clock\") itself.\n" + "> > ?[2] We'll use whatever reference clock value is given.\n" + "> > ?????I.e. we'll be able to do a fix-up of that reference clock\n" + "> > ?????value early in platform code depending on HW we're running on.\n" + "> > ?????That's what people do here and there.\n" + "> > ?[3] Remember another clock driver for AXS10x board is right around\n" + "> > ?????the corner. I mean the one for ARC PGU which uses exactly the same\n" + "> > ?????master clock. So one fixup as mentioned above will work\n" + "> > ?????at once for 2 clock drivers.\n" "> > \n" "> > Let me know if above makes sense.\n" "> That approach can't be used because the reference clock value will change in the\n" - "> next firmware release.\302\240\302\240The new release will have a reference clock of 28224000\n" + "> next firmware release.??The new release will have a reference clock of 28224000\n" "> Hz instead of the usual 27000000 Hz, so we need to have a way to distinguish\n" "> between them. Because of that we can't have only one master clock unless you\n" "> state to users that they have to change the reference clock value when using the\n" @@ -89,7 +83,7 @@ "Ok reference clock will change.\n" "But I may guess we'll still be able to determine at least that new\n" "firmware version in run-time, right? If so we'll update a fix-up in\n" - "early axs10x platform code so that reference clock will be set as\302\24028224000 Hz.\n" + "early axs10x platform code so that reference clock will be set as?28224000 Hz.\n" "\n" "And indeed 2 DT files is a no go - we want to run the same one binary\n" "(with built-in .dtb) on all flavors of AXS boards. And fix-up I'm talking about\n" @@ -98,4 +92,4 @@ "\n" -Alexey -040e06b9d820ab252013f4b5274ed1a1b51d32e2b8b0f4c9ae98c6fd86f1a8aa +64dae6e9d94d758592c76d1f5326d7dd5bd5491e724f6a97b6ac98b2760238ac
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