From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mika Kahola Subject: Re: [PATCH 1/3] drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency Date: Wed, 27 Apr 2016 11:19:27 +0300 Message-ID: <1461745167.30256.4.camel@sorvi> References: <1461689194-6079-1-git-send-email-ville.syrjala@linux.intel.com> <1461689194-6079-2-git-send-email-ville.syrjala@linux.intel.com> Reply-To: mika.kahola@intel.com Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 86BAE6EA24 for ; Wed, 27 Apr 2016 08:19:29 +0000 (UTC) In-Reply-To: <1461689194-6079-2-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org SW5kZWVkLCBCU3BlYyBzYXlzIHRoYXQgdGhpcyByZWdpc3RlciBzaG91bGQgYmUgcHJvZ3JhbW1l ZCBieSBDRCBjbG9jawptaW51cyBvbmUuCgpSZXZpZXdlZC1ieTogTWlrYSBLYWhvbGEgPG1pa2Eu a2Fob2xhQGludGVsLmNvbT4KCk9uIFR1ZSwgMjAxNi0wNC0yNiBhdCAxOTo0NiArMDMwMCwgdmls bGUuc3lyamFsYUBsaW51eC5pbnRlbC5jb20gd3JvdGU6Cj4gRnJvbTogVmlsbGUgU3lyasOkbMOk IDx2aWxsZS5zeXJqYWxhQGxpbnV4LmludGVsLmNvbT4KPiAKPiBVcGRhdGUgQ0RDTEtfRlJFUSBv biBCRFcgYWZ0ZXIgY2hhbmdpbmcgdGhlIGNkY2xrIGZyZXF1ZW5jeS4gTm90IHN1cmUKPiBpZiB0 aGlzIGlzIGEgbGF0ZSBhZGRpdGlvbiB0byB0aGUgc3BlYywgb3IgaWYgSSBzaW1wbHkgb3Zlcmxv b2tlZCB0aGlzCj4gc3RlcCB3aGVuIHdyaXRpbmcgdGhlIG9yaWdpbmFsIGNvZGUuCj4gCj4gVGhp cyBpcyB3aGF0IEJzcGVjIGhhcyB0byBzYXkgYWJvdXQgQ0RDTEtfRlJFUToKPiAiUHJvZ3JhbSB0 aGlzIGZpZWxkIHRvIHRoZSBDRCBjbG9jayBmcmVxdWVuY3kgbWludXMgb25lLiBUaGlzIGlzIHVz ZWQgdG8KPiAgZ2VuZXJhdGUgYSBkaXZpZGVkIGRvd24gY2xvY2sgZm9yIG1pc2NlbGxhbmVvdXMg dGltZXJzIGluIGRpc3BsYXkuIgo+IAo+IEFuZCB0aGUgIkJyb2Fkd2VsbCBTZXF1ZW5jZXMgZm9y IENoYW5naW5nIENEIENsb2NrIEZyZXF1ZW5jeSIgc2VjdGlvbgo+IGNsYXJpZmllcyB0aGlzIGZ1 cnRoZXI6Cj4gIkZvciBDRCBjbG9jayAzMzcuNSBNSHosIHByb2dyYW0gMzM3IGRlY2ltYWwuCj4g IEZvciBDRCBjbG9jayA0NTAgTUh6LCBwcm9ncmFtIDQ0OSBkZWNpbWFsLgo+ICBGb3IgQ0QgY2xv Y2sgNTQwIE1IeiwgcHJvZ3JhbSA1MzkgZGVjaW1hbC4KPiAgRm9yIENEIGNsb2NrIDY3NSBNSHos IHByb2dyYW0gNjc0IGRlY2ltYWwuIgo+IAo+IENjOiBzdGFibGVAdmdlci5rZXJuZWwub3JnCj4g Q2M6IE1pa2EgS2Fob2xhIDxtaWthLmthaG9sYUBpbnRlbC5jb20+Cj4gRml4ZXM6IGI0MzJlNWNm ZDVlOSAoImRybS9pOTE1OiBCRFcgY2xvY2sgY2hhbmdlIHN1cHBvcnQiKQo+IFNpZ25lZC1vZmYt Ynk6IFZpbGxlIFN5cmrDpGzDpCA8dmlsbGUuc3lyamFsYUBsaW51eC5pbnRlbC5jb20+Cj4gLS0t Cj4gIGRyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfcmVnLmggICAgICB8IDIgKysKPiAgZHJpdmVy cy9ncHUvZHJtL2k5MTUvaW50ZWxfZGlzcGxheS5jIHwgMiArKwo+ICAyIGZpbGVzIGNoYW5nZWQs IDQgaW5zZXJ0aW9ucygrKQo+IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9p OTE1X3JlZy5oIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9yZWcuaAo+IGluZGV4IDAzMjY0 ZmQzMGZkZC4uNDFjOWFlMDM2NTJiIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1 L2k5MTVfcmVnLmgKPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1X3JlZy5oCj4gQEAg LTc0ODQsNiArNzQ4NCw4IEBAIGVudW0gc2tsX2Rpc3BfcG93ZXJfd2VsbHMgewo+ICAjZGVmaW5l ICBUUkFOU19DTEtfU0VMX0RJU0FCTEVECQkoMHgwPDwyOSkKPiAgI2RlZmluZSAgVFJBTlNfQ0xL X1NFTF9QT1JUKHgpCQkoKCh4KSsxKTw8MjkpCj4gIAo+ICsjZGVmaW5lIENEQ0xLX0ZSRVEJCQlf TU1JTygweDQ2MjAwKQo+ICsKPiAgI2RlZmluZSBfVFJBTlNBX01TQV9NSVNDCQkweDYwNDEwCj4g ICNkZWZpbmUgX1RSQU5TQl9NU0FfTUlTQwkJMHg2MTQxMAo+ICAjZGVmaW5lIF9UUkFOU0NfTVNB X01JU0MJCTB4NjI0MTAKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxf ZGlzcGxheS5jIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZGlzcGxheS5jCj4gaW5kZXgg OTI5ZmQ5M2IzZTVkLi5lYTU1ZGQzMzFmYWMgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9ncHUvZHJt L2k5MTUvaW50ZWxfZGlzcGxheS5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxf ZGlzcGxheS5jCj4gQEAgLTk2NDcsNiArOTY0Nyw4IEBAIHN0YXRpYyB2b2lkIGJyb2Fkd2VsbF9z ZXRfY2RjbGsoc3RydWN0IGRybV9kZXZpY2UgKmRldiwgaW50IGNkY2xrKQo+ICAJc2FuZHlicmlk Z2VfcGNvZGVfd3JpdGUoZGV2X3ByaXYsIEhTV19QQ09ERV9ERV9XUklURV9GUkVRX1JFUSwgZGF0 YSk7Cj4gIAltdXRleF91bmxvY2soJmRldl9wcml2LT5ycHMuaHdfbG9jayk7Cj4gIAo+ICsJSTkx NV9XUklURShDRENMS19GUkVRLCBESVZfUk9VTkRfQ0xPU0VTVChjZGNsaywgMTAwMCkgLSAxKTsK PiArCj4gIAlpbnRlbF91cGRhdGVfY2RjbGsoZGV2KTsKPiAgCj4gIAlXQVJOKGNkY2xrICE9IGRl dl9wcml2LT5jZGNsa19mcmVxLAoKLS0gCk1pa2EgS2Fob2xhIC0gSW50ZWwgT1RDCgpfX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpJbnRlbC1nZnggbWFpbGlu ZyBsaXN0CkludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVl ZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com ([134.134.136.20]:11828 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752409AbcD0ITa (ORCPT ); Wed, 27 Apr 2016 04:19:30 -0400 Message-ID: <1461745167.30256.4.camel@sorvi> Subject: Re: [PATCH 1/3] drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency From: Mika Kahola Reply-To: mika.kahola@intel.com To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org Date: Wed, 27 Apr 2016 11:19:27 +0300 In-Reply-To: <1461689194-6079-2-git-send-email-ville.syrjala@linux.intel.com> References: <1461689194-6079-1-git-send-email-ville.syrjala@linux.intel.com> <1461689194-6079-2-git-send-email-ville.syrjala@linux.intel.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: Indeed, BSpec says that this register should be programmed by CD clock minus one. Reviewed-by: Mika Kahola On Tue, 2016-04-26 at 19:46 +0300, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä > > Update CDCLK_FREQ on BDW after changing the cdclk frequency. Not sure > if this is a late addition to the spec, or if I simply overlooked this > step when writing the original code. > > This is what Bspec has to say about CDCLK_FREQ: > "Program this field to the CD clock frequency minus one. This is used to > generate a divided down clock for miscellaneous timers in display." > > And the "Broadwell Sequences for Changing CD Clock Frequency" section > clarifies this further: > "For CD clock 337.5 MHz, program 337 decimal. > For CD clock 450 MHz, program 449 decimal. > For CD clock 540 MHz, program 539 decimal. > For CD clock 675 MHz, program 674 decimal." > > Cc: stable@vger.kernel.org > Cc: Mika Kahola > Fixes: b432e5cfd5e9 ("drm/i915: BDW clock change support") > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > drivers/gpu/drm/i915/intel_display.c | 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 03264fd30fdd..41c9ae03652b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7484,6 +7484,8 @@ enum skl_disp_power_wells { > #define TRANS_CLK_SEL_DISABLED (0x0<<29) > #define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29) > > +#define CDCLK_FREQ _MMIO(0x46200) > + > #define _TRANSA_MSA_MISC 0x60410 > #define _TRANSB_MSA_MISC 0x61410 > #define _TRANSC_MSA_MISC 0x62410 > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 929fd93b3e5d..ea55dd331fac 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -9647,6 +9647,8 @@ static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) > sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); > mutex_unlock(&dev_priv->rps.hw_lock); > > + I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); > + > intel_update_cdclk(dev); > > WARN(cdclk != dev_priv->cdclk_freq, -- Mika Kahola - Intel OTC