Re: ✗ Fi.CI.BAT: failure for Unduplicate CHV phy code (rev5)

From: Ander Conselvan De Oliveira <conselvan2@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: "Sarvela, Tomi P" <tomi.p.sarvela@intel.com>
Subject: Re: ✗ Fi.CI.BAT: failure for Unduplicate CHV phy code (rev5)
Date: Wed, 27 Apr 2016 16:36:13 +0300	[thread overview]
Message-ID: <1461764173.2741.5.camel@gmail.com> (raw)
In-Reply-To: <20160427132336.26408.55231@emeril.freedesktop.org>

On Wed, 2016-04-27 at 13:23 +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: Unduplicate CHV phy code (rev5)
> URL   : https://patchwork.freedesktop.org/series/5463/
> State : failure
> 
> == Summary ==
> 
> Series 5463v5 Unduplicate CHV phy code
> http://patchwork.freedesktop.org/api/1.0/series/5463/revisions/5/mbox/
> 
> Test drv_module_reload_basic:
>                 dmesg-warn -> PASS       (snb-x220t)
> Test gem_exec_suspend:
>         Subgroup basic-s3:
>                 fail       -> PASS       (snb-x220t)
> Test kms_pipe_crc_basic:
>         Subgroup hang-read-crc-pipe-a:
>                 pass       -> DMESG-WARN (snb-dellxps)

[  303.915830] ------------[ cut here ]------------
[  303.915859] WARNING: CPU: 5 PID: 6657 at drivers/gpu/drm/i915/intel_display.c:13529 intel_atomic_commit+0x1271/0x1400 [i915]
[  303.915861] pipe A vblank wait timed out

https://bugs.freedesktop.org/show_bug.cgi?id=95125

>         Subgroup suspend-read-crc-pipe-a:
>                 pass       -> INCOMPLETE (hsw-gt2)

dmesg ends with

[  505.669959] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-A

Seems very unlikely this would be caused by this series. The only code that is
run on hsw machines is setting the lane count field in crtc_state, but that is
not used anywhere.

Are there any know issues with this machine?

Ander

> 
> bdw-nuci7        total:200  pass:188  dwarn:0   dfail:0   fail:0   skip:12 
> bdw-ultra        total:200  pass:175  dwarn:0   dfail:0   fail:0   skip:25 
> bsw-nuc-2        total:199  pass:158  dwarn:0   dfail:0   fail:0   skip:41 
> byt-nuc          total:199  pass:158  dwarn:0   dfail:0   fail:0   skip:41 
> hsw-brixbox      total:200  pass:174  dwarn:0   dfail:0   fail:0   skip:26 
> hsw-gt2          total:199  pass:176  dwarn:0   dfail:0   fail:1   skip:21 
> ilk-hp8440p      total:200  pass:139  dwarn:0   dfail:0   fail:0   skip:61 
> ivb-t430s        total:200  pass:169  dwarn:0   dfail:0   fail:0   skip:31 
> skl-i7k-2        total:200  pass:173  dwarn:0   dfail:0   fail:0   skip:27 
> skl-nuci5        total:200  pass:189  dwarn:0   dfail:0   fail:0   skip:11 
> snb-dellxps      total:200  pass:157  dwarn:1   dfail:0   fail:0   skip:42 
> snb-x220t        total:200  pass:158  dwarn:0   dfail:0   fail:1   skip:41 
> 
> Results at /archive/results/CI_IGT_test/Patchwork_2090/
> 
> 4fa405ab5848b76c8568c7fb771d389a6695108c drm-intel-nightly: 2016y-04m-27d-10h
> -47m-35s UTC integration manifest
> 9e163c0 drm/i915: Move VLV HDMI lane reset work around logic to
> intel_dpio_phy.c
> b7b843d drm/i915: Unduplicate pre encoder enabling phy code
> 4165303 drm/i915: Unduplicate VLV phy pre pll enabling code
> 7241e40 drm/i915: Unduplicate VLV signal level code
> 1879a24 drm/i915: Unduplicate CHV encoders' post pll disable code
> 3b54e74 drm/i915: Unduplicate CHV pre-encoder enabling phy logic
> 66e88ec drm/i915: Unduplicate CHV phy-releated pre pll enabling code
> 8a2b013 drm/i915: Unduplicate chv_data_lane_soft_reset()
> 4a6d52d drm/i915: Unduplicate CHV signal level code
> 5a20188 drm/i915: Set crtc_state->lane_count for HDMI
> 
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