From: Ander Conselvan De Oliveira <conselvan2@gmail.com>
To: Tomi Sarvela <tomi.p.sarvela@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: ✗ Fi.CI.BAT: failure for Unduplicate CHV phy code (rev5)
Date: Fri, 29 Apr 2016 10:24:40 +0300 [thread overview]
Message-ID: <1461914680.2685.6.camel@gmail.com> (raw)
In-Reply-To: <4779737.mmujrAagpL@fractal>
On Wed, 2016-04-27 at 17:39 +0300, Tomi Sarvela wrote:
> Hello,
>
> On Wednesday 27 April 2016 16:36:13 Ander Conselvan De Oliveira wrote:
> > > Subgroup suspend-read-crc-pipe-a:
> > > pass -> INCOMPLETE (hsw-gt2)
> >
> > dmesg ends with
> >
> > [ 505.669959] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-A
> >
> > Seems very unlikely this would be caused by this series. The only code that
> > is run on hsw machines is setting the lane count field in crtc_state, but
> > that is not used anywhere.
> >
> > Are there any know issues with this machine?
>
> There is no known issues with this hardware itself. There is one known issue
> with HSW and drm-intel kernel, which has taken a while to figure out. I think
> it still exists in the baseline kernel where patch is applied.
>
> (It's hard to replicate with IGT, but newest Mesa seems to hit it quite
> regularly).
Patches pushed to dinq.
Thanks,
Ander
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prev parent reply other threads:[~2016-04-29 7:24 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-27 12:44 [PATCH v4 00/10] Unduplicate CHV phy code Ander Conselvan de Oliveira
2016-04-27 12:44 ` [PATCH v4 01/10] drm/i915: Set crtc_state->lane_count for HDMI Ander Conselvan de Oliveira
2016-04-27 12:44 ` [PATCH v4 02/10] drm/i915: Unduplicate CHV signal level code Ander Conselvan de Oliveira
2016-04-27 12:44 ` [PATCH v4 03/10] drm/i915: Unduplicate chv_data_lane_soft_reset() Ander Conselvan de Oliveira
2016-04-27 12:44 ` [PATCH v4 04/10] drm/i915: Unduplicate CHV phy-releated pre pll enabling code Ander Conselvan de Oliveira
2016-04-27 12:44 ` [PATCH v4 05/10] drm/i915: Unduplicate CHV pre-encoder enabling phy logic Ander Conselvan de Oliveira
2016-04-27 12:44 ` [PATCH v4 06/10] drm/i915: Unduplicate CHV encoders' post pll disable code Ander Conselvan de Oliveira
2016-04-27 12:44 ` [PATCH v4 07/10] drm/i915: Unduplicate VLV signal level code Ander Conselvan de Oliveira
2016-04-27 12:44 ` [PATCH v4 08/10] drm/i915: Unduplicate VLV phy pre pll enabling code Ander Conselvan de Oliveira
2016-04-27 12:44 ` [PATCH v4 09/10] drm/i915: Unduplicate pre encoder enabling phy code Ander Conselvan de Oliveira
2016-04-27 12:44 ` [PATCH v4 10/10] drm/i915: Move VLV HDMI lane reset work around logic to intel_dpio_phy.c Ander Conselvan de Oliveira
2016-04-27 13:23 ` ✗ Fi.CI.BAT: failure for Unduplicate CHV phy code (rev5) Patchwork
2016-04-27 13:36 ` Ander Conselvan De Oliveira
2016-04-27 14:39 ` Tomi Sarvela
2016-04-29 7:24 ` Ander Conselvan De Oliveira [this message]
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