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[81.231.233.234]) by smtp.gmail.com with ESMTPSA id e8sm16698584wjm.23.2016.05.19.15.54.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 May 2016 15:54:26 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Fri, 20 May 2016 00:54:18 +0200 Message-Id: <1463698459-31312-5-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1463698459-31312-1-git-send-email-edgar.iglesias@gmail.com> References: <1463698459-31312-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-arm] [PATCH v1 4/5] xlnx-zynqmp: Delay realization of GIC until post CPU realization X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, alistair.francis@xilinx.com Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: tyoZRHSuUTRY From: "Edgar E. Iglesias" Delay the realization of the GIC until after CPUs are realized. This is needed for KVM as the in-kernel GIC model will fail if it is realized with no available CPUs. Signed-off-by: Edgar E. Iglesias --- hw/arm/xlnx-zynqmp.c | 56 +++++++++++++++++++++++++++++----------------------- 1 file changed, 31 insertions(+), 25 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index c180206..0648028 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -258,33 +258,9 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS); - object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); - for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { - SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); - const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; - MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index); - uint32_t addr = r->address; - int j; - - sysbus_mmio_map(gic, r->region_index, addr); - - for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { - MemoryRegion *alias = &s->gic_mr[i][j]; - - addr += XLNX_ZYNQMP_GIC_REGION_SIZE; - memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, - 0, XLNX_ZYNQMP_GIC_REGION_SIZE); - memory_region_add_subregion(system_memory, addr, alias); - } - } + /* Realize APUs before realizing the GIC. KVM requires this. */ for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { - qemu_irq irq; char *name; object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, @@ -310,6 +286,36 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) error_propagate(errp, err); return; } + } + + object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); + for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { + SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); + const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; + MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index); + uint32_t addr = r->address; + int j; + + sysbus_mmio_map(gic, r->region_index, addr); + + for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { + MemoryRegion *alias = &s->gic_mr[i][j]; + + addr += XLNX_ZYNQMP_GIC_REGION_SIZE; + memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, + 0, XLNX_ZYNQMP_GIC_REGION_SIZE); + memory_region_add_subregion(system_memory, addr, alias); + } + } + + for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { + qemu_irq irq; sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), -- 2.5.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45857) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b3Wpq-0008Ms-Kt for qemu-devel@nongnu.org; Thu, 19 May 2016 18:54:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b3Wpo-0007GS-AH for qemu-devel@nongnu.org; Thu, 19 May 2016 18:54:29 -0400 From: "Edgar E. Iglesias" Date: Fri, 20 May 2016 00:54:18 +0200 Message-Id: <1463698459-31312-5-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1463698459-31312-1-git-send-email-edgar.iglesias@gmail.com> References: <1463698459-31312-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v1 4/5] xlnx-zynqmp: Delay realization of GIC until post CPU realization List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: alistair.francis@xilinx.com, crosthwaite.peter@gmail.com, peter.maydell@linaro.org, edgar.iglesias@xilinx.com, qemu-arm@nongnu.org From: "Edgar E. Iglesias" Delay the realization of the GIC until after CPUs are realized. This is needed for KVM as the in-kernel GIC model will fail if it is realized with no available CPUs. Signed-off-by: Edgar E. Iglesias --- hw/arm/xlnx-zynqmp.c | 56 +++++++++++++++++++++++++++++----------------------- 1 file changed, 31 insertions(+), 25 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index c180206..0648028 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -258,33 +258,9 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS); - object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); - for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { - SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); - const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; - MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index); - uint32_t addr = r->address; - int j; - - sysbus_mmio_map(gic, r->region_index, addr); - - for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { - MemoryRegion *alias = &s->gic_mr[i][j]; - - addr += XLNX_ZYNQMP_GIC_REGION_SIZE; - memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, - 0, XLNX_ZYNQMP_GIC_REGION_SIZE); - memory_region_add_subregion(system_memory, addr, alias); - } - } + /* Realize APUs before realizing the GIC. KVM requires this. */ for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { - qemu_irq irq; char *name; object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, @@ -310,6 +286,36 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) error_propagate(errp, err); return; } + } + + object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); + for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { + SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); + const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; + MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index); + uint32_t addr = r->address; + int j; + + sysbus_mmio_map(gic, r->region_index, addr); + + for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { + MemoryRegion *alias = &s->gic_mr[i][j]; + + addr += XLNX_ZYNQMP_GIC_REGION_SIZE; + memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, + 0, XLNX_ZYNQMP_GIC_REGION_SIZE); + memory_region_add_subregion(system_memory, addr, alias); + } + } + + for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { + qemu_irq irq; sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), -- 2.5.0